Programming The Pll - Freescale Semiconductor MC68HC08KH12 Datasheet

8.4.6 Programming the PLL

Advance Information
94
noise hit and the software must take appropriate action, depending on
the application. (See 8.7 Interrupts
using interrupts.) The following conditions apply when the PLL is in
automatic bandwidth control mode:
• The ACQ bit (See
(PBWC).) is a read-only indicator of the mode of the filter. (See
8.4.4 Acquisition and Tracking
• The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆
, and is cleared when the VCO frequency is out of
TRK
a certain tolerance, ∆
Specifications
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆
LOCK
a certain tolerance ∆
Specifications
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's
lock condition changes, toggling the LOCK bit. (See
Control Register
The following procedure shows how to program the PLL.
1. Choose the desired bus frequency, f
The relationship between the VCO frequency f
frequency f is
BUS
The VCO frequency need to be at 48MHz for the USB module
reference clock.
Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHz,
3MHz, or 1.5MHz respectively.
for information and precautions on
8.6.2 PLL Bandwidth Control Register
Modes.)
. (See 8.9 Acquisition/Lock Time
UNT
for more information.)
, and is cleared when the VCO frequency is out of
. (See 8.9 Acquisition/Lock Time
UNL
for more information.)
(PCTL).)
BUS
f
VCLK ×
------------- =
4 f
BUS
P
2
48MHz
×
------------------- - =
4 f
BUS
P
2
8.6.1 PLL
.
and the bus
VCLK
MC68HC(7)08KH12 Rev. 1.1
—
Freescale Semiconductor