Freescale Semiconductor MC68HC08KH12 Datasheet page 82

NOTE:
CGMXCLK
INT/BREAK
IAB
Figure 7-19. Stop Mode Recovery from Interrupt or Break
Advance Information
82
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-18
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB STOP ADDR
IDB PREVIOUS DATA
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD
STOP +1 STOP + 2
shows stop mode entry timing.
STOP ADDR + 1 SAME
NEXT OPCODE
STOP + 2 SP SP – 1
MC68HC(7)08KH12
SAME
SAME SAME
SP – 2 SP – 3
Rev. 1.1
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Freescale Semiconductor