Figure 236. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec - ST STM32L0x3 Reference Manual

Inter-integrated circuit (I2C) interface
that case the total number of TXIS interrupts is NBYTES-1 and the content of the
I2C_PECR register is automatically transmitted if the master requests an extra byte after the
NBYTES-1 data transfer.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 236. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC

736/1043
SMBus slave
transmission
Slave initialization
No
I2C_ISR.ADDR =
1?
Yes
Read ADDCODE and DIR in I2C_ISR
I2C_CR2.NBYTES = N + 1
PECBYTE=1
Set I2C_ICR.ADDRCF
I2C_ISR.TXIS
=1?
Yes
Write I2C_TXDR.TXDATA
RM0367 Rev 7
SCL
stretched
No
RM0367
MS19867V2