Counter Modes; Upcounting Mode; Figure 154. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - ST STM32L0x3 Reference Manual

RM0367

Figure 154. Counter timing diagram with prescaler division change from 1 to 4

Timerclock = CK_CNT
Update event (UEV)
Prescaler control register
Prescaler counter
22.3.2

Counter modes

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller on TIM21/22) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
CK_PSC
CEN
Counter register
Write a new value in TIMx_PSC
Prescaler buffer
F7 F8 F9 FA FB
FC
0
0
0
RM0367 Rev 7
General-purpose timers (TIM21/22)
00
3
3
0 1 2 3 0
01
1 2 3
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