Tim21/22 Control Register 2 (Timx_Cr2) - ST STM32L0x3 Reference Manual

RM0367
22.4.2

TIM21/22 control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Reserved
111: Reserved
Bits 3:0 Reserved, must be kept at reset value.
12 11 10 9
Res. Res. Res.
8 7 6
Res. Res. MMS[2:0]
rw
RM0367 Rev 7
General-purpose timers (TIM21/22)
5 4 3 2
Res. Res.
rw rw
1 0
Res. Res.
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