ST STM32L0x3 Reference Manual page 1030

Revision history
Date
19-Feb-2016
1030/1043
Table 181. Document revision history (continued)
Revision
Liquid crystal display controller (LCD)
Updated Section : LCD intermediate voltages, Section : LCD drive
selection and Section : External decoupling.
Updated Figure 72: SEG/COM mux feature example
Updated LCDEN bit description in LCD control register (LCD_CR).
Touch sensing controller (TSC)
Removed Section Capacitive sensing GPIOs.
Added note in Section 18.3.4: Charge transfer acquisition sequence.
Added notes in CTPL and PGPSC bit description in Section 18.6.1:
TSC control register (TSC_CR).
TIMER2/3
Updated ETR_RMP bit definition in TIM2 option register (TIM2_OR).
TIMER21/22
Updated SMS bit definition in Section 22.4.3: TIM21/22 slave mode
control register (TIMx_SMCR).
Restricted Table 103: TIM21/22 register map and reset values to 16
bits instead of 32.
4
TIMER6/7
(continued)
Restricted Table 104: TIM6/7 register map and reset values to 16 bits
instead of 32.
Low-power timer (LPTIM)
Updated Section 24.4.7: Operating mode.
Added Section Figure 197.: LPTIM output waveform, single counting
mode configuration, Section Figure 198.: LPTIM output waveform,
Single counting mode configuration and Set-once mode activated
(WAVE bit is set) and Section Figure 199.: LPTIM output waveform,
Continuous counting mode configuration.
Updated CNT bitfield definition in Section 24.6.8: LPTIM counter
register (LPTIM_CNT).
Removed LPTIM1_OR and LPTIM2_OR.
Real-time clock (RTC)
Updated note below Figure 202: RTC block diagram.
Updated step 3 in Section : Programming the wakeup timer.
Updated behavior of RTC under system reset in Section 27.4.9:
Resetting the RTC.
Modified WUTWF description in Section 27.7.4: RTC initialization and
status register (RTC_ISR).
RM0367 Rev 7
Changes
RM0367