Wwdg Register Map; Table 115. Wwdg Register Map And Reset Values - ST STM32L0x3 Reference Manual

System window watchdog (WWDG)
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
26.5.4

WWDG register map

The following table gives the WWDG register map and reset values.
Offset Register
WWDG_CR
0x000
Reset value
WWDG_CFR
0x004
Reset value
WWDG_SR
0x008
Reset value
Refer to
650/1043
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing '0'. Writing '1' has no effect. This bit is also set if the interrupt is not
enabled.

Table 115. WWDG register map and reset values

Section 2.2 on page 58 for the register boundary addresses.
RM0367 Rev 7
RM0367
T[6:0]
0 1 1 1 1 1 1
W[6:0]
0 0 0 1 1 1 1 1 1
1
1
0