ST STM32L0x3 Reference Manual page 1005

RM0367
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
/* (7) Set capture compare register to a value between 0 and 99 */
TIMx->CR2
TIMx->CCMR1
TIMy->SMCR
TIMx->PSC
TIMy->PSC
TIMx->ARR
TIMx->
/* Configure the slave timer Channel 1 as PWM as Timer to show
synchronicity */
/* (1) Configure the Timer y in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMx Autoreload to 99 */
/* (3) Set capture compare register to 25 */
TIMy->CCMR1
TIMy->ARR
TIMy->
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
/* (2) Enable output (MOE = 1 */
TIMx->CCER
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
/* (2) Enable output (MOE = 1 */
TIMy->CCER
/* (1) Reset Timer x by writing '1 in UG bit (TIMx_EGR register) */
/* (2) Reset Timer y by writing '1 in UG bit (TIMy_EGR register) */
TIMx->EGR
TIMy->EGR
/* (1) Enable the slave counter first by writing CEN=1
/* (2) Start the master counter by writing CEN=1 in the TIMx_CR1
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the
TIMy_SMCR register. */
each 10ms */
|= TIM_CR2_MMS_0;
|= TIM_CCMR1_OC1M_2
|= TIM_SMCR_SMS_2
= 2; /* (4) */
= 2; /* (5) */
= 99; /* (6) */
CCR1 = 25; /* (7) */
|= TIM_CCMR1_OC1M_2
= 99; /* (2) */
CCR1 = 25; /* (3) */
enable the output on OC1 (CC1E = 1 */
|= TIM_CCER_CC1E;
enable the output on OC1 (CC1E = 1 */
|= TIM_CCER_CC1E;
|= TIM_EGR_UG;
|= TIM_EGR_UG;
in the TIMy_CR1 register.
TIMy will start synchronously with the master timer*/
register. */
/* (1 */
| TIM_CCMR1_OC1M_1;
| TIM_SMCR_SMS_0;
| TIM_CCMR1_OC1M_1;
RM0367 Rev 7
Code examples
/* (2) */
/* (3) */
/* (1) */
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