ST STM32L0x3 Reference Manual page 988

Code examples
/* Performs the AD conversion */
ADC1->CR
while ((ADC1->ISR
{
/* For robust implementation, add here time-out management */
}
A.8.6 Continuous conversion sequence code example
/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the continuous mode and scanning direction */
/* (3) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
/* (5) Enable interrupts on EOC, EOSEQ and overrrun */
/* (6) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1
ADC1->CHSELR
ADC1->SMPR
ADC1->IER
ADC->CCR
/* Configure NVIC for ADC */
/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC */
NVIC_EnableIRQ(ADC1_COMP_IRQn);
NVIC_SetPriority(ADC1_COMP_IRQn,0);
A.8.7 Single conversion sequence code example
/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on falling edge and external trigger on
/* (3) Select CHSEL17 for VRefInt */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
/* (5) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1
ADC1->CHSELR
ADC1->SMPR
ADC->CCR
Note: Then TIM22 must be configured to generate an external trigger on TRG0
988/1043
|= ADC_CR_ADSTART;
& ADC_ISR_EOC) == 0)
than 5 us */
|= ADC_CFGR1_WAIT |ADC_CFGR1_CONT
= ADC_CHSELR_CHSEL4
| ADC_CHSELR_CHSEL17;
|= ADC_SMPR_SMP_0
= ADC_IER_EOCIE
|= ADC_CCR_VREFEN;
TIM22_TRGO by selecting TRG4 (EXTSEL = 100) */
than 5us */
|= ADC_CFGR1_EXTEN_0
= ADC_CHSELR_CHSEL17;
|= ADC_SMPR_SMP_0
|= ADC_CCR_VREFEN;
/* start the ADC conversion */
/* wait end of conversion */
| ADC_CHSELR_CHSEL9 \
/* (3) */
| ADC_SMPR_SMP_1
| ADC_IER_EOSEQIE
/* (6) */
/* (1) */
/* (2) */
| ADC_CFGR1_EXTSEL_2
/* (3) */
| ADC_SMPR_SMP_1
/* (5) */
RM0367 Rev 7
- Software trigger
| ADC_CFGR1_SCANDIR;/* (2) */
| ADC_SMPR_SMP_2;
| ADC_IER_OVRIE; /* (5) */
- Hardware trigger
; /* (2) */
| ADC_SMPR_SMP_2;
periodically.
RM0367
/* (4) */
/* (4) */