ST STM32L0x3 Reference Manual page 858

Low-power universal asynchronous receiver transmitter (LPUART)
30.7 LPUART registers
Refer to
The peripheral registers have to be accessed by words (32 bits).
30.7.1 Control register 1 (LPUART_CR1)
Address offset: 0x00
Reset value: 0x0000
31 30 29
Res. Res. Res.
15 14 13
Res. CMIE MME
rw rw
Bits 31:29 Reserved, must be kept at reset value
Bit 28 M1: Word length
This bit, with bit 12 (M0) determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the LPUART is disabled (UE=0).
Bit 27 Reserved, must be kept at reset value
Bit 26 Reserved, must be kept at reset value
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in UCLK (USART clock) clock cycles. For more
details, refer to RS485 Driver Enable paragraph.
This bit field can only be written when the LPUART is disabled (UE=0).
Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in UCLK
(USART clock) clock cycles. For more details, refer to RS485 Driver Enable paragraph.
If the LPUART_TDR register is written during the DEDT time, the new data is transmitted
only when the DEDT and DEAT times have both elapsed.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 15 Reserved, must be kept at reset value
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register.
858/1043
Section 1.2 on page 52
28 27 26 25
M1 Res. Res.
rw rw
12 11 10 9
M0 WAKE PCE PS
rw rw rw rw
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
rw rw rw
8 7 6
PEIE TXEIE TCIE RXNEIE IDLEIE
rw rw rw
RM0367 Rev 7
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3 2
TE RE
rw rw rw rw
RM0367
17 16
rw rw
1 0
UESM UE
rw rw