ST STM32L0x3 Reference Manual page 908

Serial peripheral interface/ inter-IC sound (SPI/I2S)
set after each transfer from the Tx buffer to the shift register and an interrupt is generated if
the TXEIE bit in the SPIx_CR2 register is set.
For more details about the write operations depending on the I
refer to Section 31.6.3: Supported audio
To ensure a continuous audio data transmission, it is mandatory to write the SPIx_DR
register with the next data to transmit before the end of the current transmission.
To switch off the I
Reception sequence
The operating mode is the same as for transmission mode except for the point 3 (refer to the
procedure described in
set the master reception mode through the I2SCFG[1:0] bits.
Whatever the data or channel length, the audio data are received by 16-bit packets. This
means that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated
if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length
configuration, the audio value received for a right or left channel may result from one or two
receptions into the Rx buffer.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the
2
I S cell.
For more details about the read operations depending on the I
refer to Section 31.6.3: Supported audio
If data are received while the previously received data have not been read yet, an overrun is
generated and the OVR flag is set. If the ERRIE bit is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I
transfer cycle properly without initiating a new data transfer. The sequence depends on the
configuration of the data and channel lengths, and on the audio protocol mode selected. In
the case of:
•
16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1)
using the LSB justified mode (I2SSTD = 10)
a)
b)
c)
•
16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in
MSB justified, I
respectively)
a)
b)
c)
908/1043
2
S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.
Section 31.6.5: I
2
S, specific actions are required to ensure that the I
Wait for the second to last RXNE = 1 (n – 1)
2
Then wait 17 I S clock cycles (using a software loop)
2
Disable the I S (I2SE = 0)
2
S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11,
Wait for the last RXNE
2
Then wait 1 I S clock cycle (using a software loop)
2
Disable the I S (I2SE = 0)
protocols).
2
S master mode), where the configuration should
protocols.
RM0367 Rev 7
RM0367
2
S Standard-mode selected,
2
S Standard-mode selected,
2
S completes the