Lcd Frame Control Register (Lcd_Fcr) - ST STM32L0x3 Reference Manual

RM0367
Note: The VSEL, MUX_SEG,BIAS, and DUTY bits are write-protected when the LCD is enabled
(ENS bit in LCD_SR to 1).
17.7.2

LCD frame control register (LCD_FCR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
BLINKF[2:0]
rw rw rw rw
Bits 31:26 Reserved, must be kept at reset value
Bits 25:22 PS[3:0]: PS 16-bit prescaler
These bits are written by software to define the division factor of the PS 16-bit prescaler.
ck_ps = LCDCLK/(2). See
1111:ck_ps = LCDCLK/32768
Bits 21:18 DIV[3:0]: DIV clock divider
These bits are written by software to define the division factor of the DIV divider. See
Section
1111:ck_div = ck_ps/31
Bits 17:16 BLINK[1:0]: Blink mode selection
Bits 15:13 BLINKF[2:0]: Blink frequency selection
27 26 25
Res. Res.
rw
11 10 9
CC[2:0]
rw rw rw
0000: ck_ps = LCDCLK
0001: ck_ps = LCDCLK/2
0002: ck_ps = LCDCLK/4
...
17.4.2.
0000: ck_div = ck_ps/16
0001: ck_div = ck_ps/17
0002: ck_div = ck_ps/18
...
00: Blink disabled
01: Blink enabled on SEG[0], COM[0] (1 pixel)
10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty)
11: Blink enabled on all SEGs and all COMs (all pixels)
000: f /8
LCD
001: f /16
LCD
010: f /32
LCD
011: f /64
LCD
100: f /128
LCD
101: f /256
LCD
110: f /512
LCD
111: f /1024
LCD
Liquid crystal display controller (LCD)
24 23 22
PS[3:0]
rw rw rw
8 7 6
DEAD[2:0] PON[2:0]
rw rw rw
Section 17.4.2.
RM0367 Rev 7
21 20 19 18
DIV[3:0]
rw rw rw rw
5 4 3 2
UDDIE Res.
rw rw rw
17 16
BLINK[1:0]
rw rw
1 0
SOFIE HD
rw rw
407/1043
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