Pwm Edge-Aligned Mode; Figure 136. Edge-Aligned Pwm Waveforms (Arr=8) - ST STM32L0x3 Reference Manual

General-purpose timers (TIM2/TIM3)
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be
cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:
•
When the result of the comparison changes, or
•
When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the "frozen" configuration (no comparison, OCxM='000) to one of the PWM modes
(OCxM='110 or '111).
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
Upcounting mode on page
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at '1.
If the compare value is 0 then OCxREF is held at '0.
PWM waveforms in an example where TIMx_ARR=8.
For code example, refer to
CCRx=4
CCRx=8
CCRx>8
CCRx=0
504/1043
483.
A.11.8: Edge-aligned PWM configuration

Figure 136. Edge-aligned PWM waveforms (ARR=8)

0
Counter register
OCXREF
CCxIF
OCXREF
CCxIF
'1'
OCXREF
CCxIF
'0'
OCXREF
CCxIF
Figure 136
1 2 3 4 5
RM0367 Rev 7
Section :
shows some edge-aligned
example.
6 7 8 0 1
RM0367
MS31093V1