ST STM32L0x3 Reference Manual page 1004

Code examples
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
/* (7) Set capture compare register to a value between 0 and 999 */
TIMx->CR2
TIMx->CCMR1
TIMy->SMCR
TIMx->PSC
TIMy->PSC
TIMx->ARR
TIMx->
/* Configure the slave timer to generate toggling on each count */
/* (1) Configure the Timer 2 in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMx Autoreload to 1 */
/* (3) Set capture compare register to 1 */
TIMy->CCMR1
TIMy->ARR
TIMy->
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
/* (2) Enable output (MOE = 1 */
TIMx->CCER
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
/* (2) Enable output (MOE = 1 */
TIMy->CCER
/* (1) Enable the slave counter first by writing CEN=1 in the TIMy_CR1
/* (2) Enable the master counter by writing CEN=1 in the TIMx_CR1
TIMy->CR1
TIMx->CR1
A.11.19 Master and slave synchronization code example
/* (1) Configure Timer x in master mode to send its enable signal
/* (2) Configure the Timer x Channel 1 waveform (TIMx_CCMR1 register)
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TIMy_SMCR register. */
each 100ms */
|= TIM_CR2_MMS_2;
|= TIM_CCMR1_OC1M_2
|= TIM_SMCR_SMS_2
= 2; /* (4) */
= 2; /* (5) */
= 999; /* (6) */
CCR1 = 700; /* (7) */
|= TIM_CCMR1_OC1M_2
= 1; /* (2) */
CCR1 = 1; /* (3) */
enable the output on OC1 (CC1E = 1 */
|= TIM_CCER_CC1E;
enable the output on OC1 (CC1E = 1 */
|= TIM_CCER_CC1E;
register. */
register. */
|= TIM_CR1_CEN;
|= TIM_CR1_CEN;
as trigger output (MMS=001 in the TIMx_CR2 register). */
is in PWM mode 1 (write OC1M = 110) */
/* (1 */
| TIM_CCMR1_OC1M_1;
| TIM_SMCR_SMS_0;
| TIM_CCMR1_OC1M_1;
/* (1) */
/* (2) */
RM0367 Rev 7
/* (2) */
/* (3) */
/* (1) */
RM0367