ST STM32L0x3 Reference Manual page 1034

Ultra-low-power advanced arm-based 32-bit mcus
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Revision history
Date
14-Nov-2016
1034/1043
Table 181. Document revision history (continued)
Revision
General-purpose timers (TIM2/3)
Replace TIM2_SMCR by TIMy_SMCR in Section : Using one timer to
start another timer and Section : Starting 2 timers synchronously in
response to an external trigger.
Updated PSC[15:0] bitfield definition in Section 21.4.11: TIMx
prescaler (TIMx_PSC).
Changed TIMx capture/compare register 1 (TIMx_CCR1), TIMx
capture/compare register 2 (TIMx_CCR2), TIMx capture/compare
register 3 (TIMx_CCR3) and TIMx capture/compare register 4
(TIMx_CCR4) registers to read-only when CCy channel is configured
as input.
Replace USB_OE by USB_NOE in TIM3 option register (TIM3_OR).
Lite timers (TIM21/22)
Updated PSC[15:0] bitfield definition in Section 22.4.10: TIM21/22
prescaler (TIMx_PSC).
Changed TIMx_ARR reset value to 0xFFFF FFFF in Section 22.4.11.
Changed TIM21/22 control register 1 (TIMx_CR1) and TIM21/22
control register 2 (TIMx_CR2) registers to read-only when CCy
channel is configured as input.
Basic timers (TIM6/7)
5
Updated PSC[15:0] bitfield definition in Section 23.4.7: TIM6/7
(continued)
prescaler (TIMx_PSC).
Changed TIMx_ARR reset value to 0xFFFF FFFF in Section 23.4.8.
Real-time clock (RTC)
Replaced HSE/32 by HSE prescaled in Figure 202: RTC block
diagram.
Added Section 27.3: RTC implementation. Removed notes related to
RTC_TAMP3 availability depending on categories in RTC_ISR and
RTC_TAMPCR.
Updated Section 27.4.15: Calibration clock output.
Section 27.7.3: RTC control register (RTC_CR):
Added caution note at the end of the section.
Updated ADD1H and SUB1H descriptions
Updated caution note at the end of Section 27.7.16: RTC tamper
configuration register (RTC_TAMPCR).
Updated RTC backup registers (RTC_BKPxR) register description.
Inter-integrated circuit interface (I2C)
Updated Section 28.4.5: I2C initialization, Section 28.4.8: I2C slave
mode and Section 28.7.5: Timing register (I2C_TIMINGR).
Updated:
Note on Section 28.4.9: I2C master mode
Bit 13 on Section 28.7.2: Control register 2 (I2C_CR2)
RM0367 Rev 7
Changes
RM0367

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