Write Protection Register 2 (Flash_Wrprot2) - ST STM32L0x3 Reference Manual

RM0367
3.7.10

Write protection register 2 (FLASH_WRPROT2)

Address offset: 0x80
Reset value: 0x 0000 XXXX. It depends on the value programmed in the option bytes.
During production, it is set to 0x0000 0000.
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 WRPROT2: Write protection
– If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection
– If WPRMOD = 1, these bits are used to protect from reading as data (see
When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing
the relative Option bytes.
When WPRMOD = 1, it is only possible to increase the protection, which means that the user
can add zeros but cannot add ones.
The mass erase deletes the WPRMOD bits but does not delete the content of this register.
After a mass erase, the user must write the relative Option bytes with zeros to remove
completely the write protections.
If there is a mismatch on this configuration during the Option bytes loading, and the content of
WPRMOD in the FLASH_OPTR register is:
If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus
loaded with ones), the register is loaded with 0x0000.
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
configuration for the Flash memory (every bit protects a 4-Kbyte sector: the first bit protects
the first sector, the second bit protects the second page and so on). In this case, 1 = sector
protected, 0 = no protection.
pre-read), and then also from writing, with the same granularity and with the same
combination of bits and sectors. The read protection does not protect against a fetch. In this
case, 1 = no protection, 0 = sector protected.
1, this configuration is loaded with 0x0000.
0, this configuration is loaded with 0xFFFF.
Flash program memory and data EEPROM (FLASH)
24 23 22
Res. Res. Res. Res.
8 7 6
WRPROT2 [15:0]
r r r
RM0367 Rev 7
21 20 19 18
Res. Res. Res.
5 4 3 2
r r r r
Read as data and
17 16
Res. Res.
1 0
r r
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