Figure 274. Reception Using Dma; Figure 275. Hardware Flow Control Between 2 Lpuarts - ST STM32L0x3 Reference Manual

RM0367
TX line
RXNE flag
DMA request
LPUART_RDR
DMA reads
LPUART_RDR
DMA TCIF flag
(transfer complete)
Software configures
the DMA to receive 3
datablocks and
enables the LPUART
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the LPUART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
30.4.10 RS232 Hardware flow control and RS485 Driver Enable
using LPUART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the LPUART_CR3 register).
Low-power universal asynchronous receiver transmitter (LPUART)

Figure 274. Reception using DMA

Frame 1
Set by hardware
cleared by DMA read
F 1
DMA reads F1
from
LPUART_RDR
Figure 263 shows how to connect 2 devices in this mode:

Figure 275. Hardware flow control between 2 LPUARTs

LPUART 1
TX
TX circuit
CTS
RX
RX circuit
RTS
RM0367 Rev 7
Frame 2
F2
DMA reads F2 DMA reads F3
from
LPUART_RDR LPUART_RDR
RX
RTS
TX
CTS
Frame 3
F3
Cleared by
Set by hardware
software
DMA transfer is
complete
from
(TCIF=1 in
DMA_ISR)
MSv31891V3
LPUART 2
RX circuit
TX circuit
MSv31892V2
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