ST STM32L0x3 Reference Manual page 169

RM0367
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software.
Bit 0 LPSDSR: Low-power deepsleep/Sleep/Low-power run
– DeepSleep/Sleep modes
– Low-power run mode
This bit is set and cleared by software.
0: No effect
1: Clear the WUF Wakeup flag after 2 system clock cycles
0: Enter Stop mode when the CPU enters Deepsleep.
1: Enter Standby mode when the CPU enters Deepsleep.
When this bit is set, the regulator switches in low-power mode when the CPU enters sleep
or Deepsleep mode. The regulator goes back to Main mode when the CPU exits from
these modes.
When this bit is set, the regulator switches in low-power mode when the bit LPRUN is set.
The regulator goes back to Main mode when the bit LPRUN is reset.
0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode
1: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode
RM0367 Rev 7
Power control (PWR)
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