ST STM32L0x3 Reference Manual page 827

RM0367
29.8.9 USART interrupt flag clear register (USART_ICR)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. EOBCF RTOCF
rc_w1
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 WUCF: Wakeup from Stop mode clear flag
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Bits 16:13 Reserved, must be kept at reset value.
Bit 12 EOBCF: End of block clear flag
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
Bit 11 RTOCF: Receiver timeout clear flag
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
Bit 10 Reserved, must be kept at reset value.
Bit 9 CTSCF: CTS clear flag
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
Bit 8 LBDCF: LIN break detection clear flag
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TCCF: Transmission complete clear flag
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Universal synchronous/asynchronous receiver transmitter (USART/UART)
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. CTSCF LBDCF
rc_w1 rc_w1
Writing 1 to this bit clears the WUF flag in the USART_ISR register.
must be kept at reset value.
Writing 1 to this bit clears the CMF flag in the USART_ISR register.
Writing 1 to this bit clears the EOBF flag in the USART_ISR register.
at reset value. Please refer to
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
must be kept at reset value. Please refer to
page 766.
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
kept at reset value. Please refer to
Writing 1 to this bit clears the LBDF flag in the USART_ISR register.
Please refer to Section 29.4: USART implementation on page
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
24 23 22
Res. Res. Res. Res.
8 7 6
Res. TCCF Res.
rc_w1 rc_w1
Section 29.4: USART implementation on page
Section 29.4: USART implementation on
Section 29.4: USART implementation on page
RM0367 Rev 7
21 20 19 18
WUCF Res. Res.
rc_w1
5 4 3 2
IDLECF ORECF NCF
rc_w1 rc_w1 rc_w1
766.
17 16
CMCF Res.
rc_w1
1 0
FECF PECF
rc_w1 rc_w1
766.
766.
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