ST STM32L0x3 Reference Manual page 1036

Revision history
Date
06-Dec-2017
1036/1043
Table 181. Document revision history (continued)
Revision
Flash program memory and data EEPROM
Updated Section 3.4: Memory protection.
Updated level 1 description in Section 3.4.1: RDP (Read Out
Protection).
Improved read while write description in Section 3.6.2: Sequence of
operations and Table 11: Boot pin and BFB2 bit configuration.
Power controller
Updated Section 6.2.3: Programmable voltage detector (PVD).
Updated Section : Exiting Standby mode.
Updated VOSF bit description in Section 6.4.2: PWR power
control/status register (PWR_CSR).
Reset and clock controller (RCC)
Updated Section 7.2.6: LSE clock.
Updated HSI16RDYF description in Section 7.3.1: Clock control
register (RCC_CR).
System configuration controller (SYSCFG)
Updated EN_VREFINT bit description in Section 10.2.3: Reference
control and status register (SYSCFG_CFGR3).
6
Direct memory controller (DMA)
Updated Section 11.3.7: DMA request mapping.
Analog-to-digital converted (ADC)
Renamed EOSEQ, EOSEQIE, EXTENSEL bits into EOS, EOSIE,
EXTEN. Replaced t
Added ADC_AWDx_OUT in Table 56: ADC internal signals.
Updated step 2 of calibration software procedure in Section 14.3.3:
Calibration (ADCAL).
Updated Section 14.3.3: Calibration (ADCAL).
Updated t
CONV
resolution.
Added note related to the management of the internal oscillator in
Section 14.6.2: Auto-off mode (AUTOFF).
Replaced ADC_HTR and ADC_LTR registers by HT[11:0] and
LT[11:0] in Section 14.7: Analog window watchdog (AWDEN,
AWDSGL, AWDCH, ADC_TR, AWD) and updated Figure 48: Analog
watchdog guarded area.
Removed all references to DMA double buffer mode.
Comparator (COMP)
Updated Figure 66: Comparator 1 and 2 block diagrams.
RM0367 Rev 7
Changes
by t in the whole document.
ADC CONV
unit in Table 61: tSAR timings depending on
RM0367