Parallel Write Half-Page Flash Program Memory - ST STM32L0x3 Reference Manual

RM0367
–
When a half-page operation starts, the memory interface waits for 16 addresses/data,
aborting (with a hard fault) all read accesses that are not a fetch (refer to
prefetch). A fetch stops the half-page operation. The memory content remains
unchanged, the FWWERR error is set in the FLASH_SR register. To complete the half-
page programming operation, all the desired values should be written again.
•
Duration
Tprog (3.2 ms).
For code example, refer to
example.

Parallel write half-page Flash program memory

•
Purpose
Write 2 half-pages (one per bank) in parallel in Flash program memory.
•
Size
Write only by word.
•
Address
For each half-page, one address, aligned to half-page start address, must be selected
in Flash program memory. The following 15 addresses must point to the half-page
selected by first address.
Furthermore, the addresses of the second half-page must be on a different bank with
respect to the start address of the first half-page (only the first address is checked).
•
Protocol
Multiple programming operation.
•
Requests
PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1, PARALLELBANK=1.
•
Errors
This operation can generate the same kind of errors as program half-page in flash
program memory. However, PGAERR is also generated when the second half-page
selected is located in the same bank as the first half-page.
All the errors detected during this operation abort the whole program operation (i.e.
both banks).
•
Description
This operation programs in parallel one half-page on both Flash program memory
banks. This speeds up the initial programming of the whole NVM.
It is possible to start with Bank 1 or Bank 2.
•
Duration
Tprog (3.2 ms).
Other categories
NOTZEROERR is set to 1. Writing a word to an address containing a non-null
value is not performed.
A.3.10: Program half-page to Flash program memory code
Flash program memory and data EEPROM (FLASH)
RM0367 Rev 7
Fetch and
91/1043
122