ST STM32L0x3 Reference Manual page 1025

RM0367 Revision history
Table 181. Document revision history (continued)
Date Revision Changes
SYSCFG
Updated Figure 1: System architecture to add STM32L07/08
peripherals.
Added USB bit in Section 10.2.1: SYSCFG memory remap register
(SYSCFG_CFGR1). Replaced REF_CFGR3 by SYSCFG_CFGR3.
Added I2C3_FMP bit and updated CAPA bits in Section 10.2.2:
SYSCFG peripheral mode configuration register (SYSCFG_CFGR2).
Updated Table 46: VLCD rails connections to GPIO pins
Updated Section 10.2.4: SYSCFG external interrupt configuration
register 1 (SYSCFG_EXTICR1), Section 10.2.5: SYSCFG external
interrupt configuration register 2 (SYSCFG_EXTICR2), Section
10.2.6: SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) and Section 10.2.7: SYSCFG external interrupt
configuration register 4 (SYSCFG_EXTICR4).
DMA
Updated DMA mapping/channel selection for category 5 devices.
INTERRUPTS
Changed number of priority levels from 16 to 4.
Updated Table 53: List of vectors and Table 54: EXTI lines
3
04-May-2015 connections to add category 5 peripherals and update vectors 17 and
(continued)
18. Added bit24 in all EXTI registers.
ADC
Updated Figure 28: ADC block diagram.
Section 13.4.1: ADC voltage regulator (ADVREGEN): changed
REF_CTRL into REF_CFGR3 and ENBUF_EN_VREFINT_ADC into
ENBUF_VREFINT_ADC.
Removed limitation related to 1.8 V VDDA minimum value. Changed
VDDA= 3.3 V into 3 V in Section 13.11: Temperature sensor and
internal reference voltage.
Changed 3.3 V into 3 V in VCHANNELx equation in Section :
Converting a supply-relative ADC measurement to an absolute
voltage value.
Updated Section 13.13: VLCD voltage monitoring.
Updated AWDCH bitfield definition in ADC_CFGR1Section 13.15.4:
ADC configuration register 1 (ADC_CFGR1).
DAC
Added dual DAC feature and DAC channel 2. Added TIM3 and TIM7
TRGO events in Table 68: External triggers.
Changed VREF+ into VDDA in Section 15.6.4: DAC output voltage.
RM0367 Rev 7 1025/1043
1039