Voltage Regulator; Dynamic Voltage Scaling Management; Range 1 - ST STM32L0x3 Reference Manual

RM0367
6.1.4

Voltage regulator

An embedded linear voltage regulator supplies all the digital circuitries except for the
Standby circuitry. The regulator output voltage (V
three different ranges within 1.2 - 1.8 V (typical) (see
The voltage regulator is always enabled after Reset. It works in three different modes: main
(MR), low-power (LPR) and power-down, depending on the application modes.
•
In Run mode, the regulator is main (MR) mode and supplies full power to the V
domain (core, memories and digital peripherals).
•
In Low-power run mode, the regulator is in low-power (LPR) mode and supplies low-
power to the V
SRAM.
•
In Sleep mode, the regulator is main (MR) mode and supplies full power to the V
domain, preserving the contents of the registers and internal SRAM.
•
In Low-power sleep mode, the regulator is in low-power (LPR) mode and supplies low-
power to the V
SRAM.
•
In Stop mode the regulator supplies low power to the V
content of registers and internal SRAM.
•
In Standby mode, the regulator is powered off. The content of the registers and SRAM
are lost except for the Standby circuitry.
6.1.5

Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (V
the circumstances.
Dynamic voltage scaling to increase V
device performance. Refer to
versus CPU performance and to the datasheet electrical characteristics for ADC clock
frequency versus dynamic range.
Dynamic voltage scaling to decrease V
save power, particularly in laptops and other mobile devices where the energy comes from a
battery and is thus limited.

Range 1

Range 1 is the "high performance" range.
The voltage regulator outputs a 1.8 V voltage (typical) as long as the V
above 1.71 V. Flash program and erase operations can be performed in this range.
The clock recovery system (CRS) is available only when the device operates in range 1
(see Section 8: Clock recovery system
When V
DD
the following conditions:
•
f
CPUfinal
•
In addition, a 5 μs delay must be respected between two changes. For example to
switch from 4.2 to 32 MHz, switch from 4.2 to 16 MHz, wait for 5 μs, then switch from
16 to 32 MHz.
domain, preserving the contents of the registers and internal
CORE
domain, preserving the contents of the registers and internal
CORE
Figure 11
is below 2.0 V, the CPU frequency changes from initial to final state must respect
< 4xf .
CPUinitial
CORE
Section
is known as overvolting. It allows improving the
CORE
for a description of the device operating conditions
is known as undervolting. It is performed to
CORE
(CRS)).
RM0367 Rev 7
Power control (PWR)
) can be programmed by software to
6.1.5).
domain, preserving the
CORE
), according to
CORE
input voltage is
DD
CORE
CORE
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