Adc_Awd1_Out Output Signal Generation; Table 64. Analog Watchdog Comparison; Table 65. Analog Watchdog Channel Selection; Figure 49. Analog Watchdog Guarded Area - ST STM32L0x3 Reference Manual

RM0367
Analog Watchdog comparison between:
Resolution
bits
Raw converted
RES[1:0]
data, left aligned
00: 12-bit DATA[11:0]
01: 10-bit DATA[11:2],00
10: 8-bit DATA[11:4],0000
11: 6-bit DATA[11:6],000000
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.
Table 65
register to enable the analog watchdog on one or more channels.
Channels guarded by the analog watchdog
None
All channels
(1)
Single
1. Selected by the AWDCH[4:0] bits
14.7.2

ADC_AWD1_OUT output signal generation

The analog watchdog is associated to an internal hardware signal, ADC_AWD1_OUT that is
directly connected to the ETR input (external trigger) of some on-chip timers (refer to the
timers section for details on how to select the ADC_AWD1_OUT signal as ETR).

Table 64. Analog watchdog comparison

Thresholds
(1)
LT[11:0] and HT[11:0]
LT[11:0] and HT[11:0]
LT[11:0] and HT[11:0]
LT[11:0] and HT[11:0]
shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1

Figure 49. Analog watchdog guarded area

Analog voltage
Higher threshold
Lower threshold

Table 65. Analog watchdog channel selection

channel
-
The user must configure LT1[1:0] and HT1[1:0] to "00"
The user must configure LT1[3:0] and HT1[3:0] to
"0000"
The user must configure LT1[5:0] and HT1[5:0] to
"000000"
Guarded area
AWDSGL bit
RM0367 Rev 7
Analog-to-digital converter (ADC)
Comments
HTx
LTx
AWDEN bit
x
0
1
MS45396V1
0
1
1
327/1043
352