Table 175. Ack Response (3 Bits); Table 176. Data Transfer (33 Bits) - ST STM32L0x3 Reference Manual

Debug support (DBG)
Bit
5
6
7
Refer to the Cortex
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.
Bit
0..2
The ACK Response must be followed by a turnaround time only if it is a READ transaction
or if a WAIT or FAULT acknowledge has been received.
Bit
0..31
32
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
33.5.3 SW-DP state machine (reset, idle states, ID code)
The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default Arm
0x0BC11477(corresponding to Cortex
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
•
The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles
• The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
•
After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Cortex
CoreSight Design Kit r1p0 TRM.
960/1043
Table 174. Packet request (8-bits) (continued)
Name
Parity Single bit parity of preceding bits
Stop 0
Not driven by the host. Must be read as "1" by the target
Park
because of the pull-up
®
-M0+ TRM for a detailed description of DPACC and APACC registers.

Table 175. ACK response (3 bits)

Name
001: FAULT
ACK
010: WAIT
100: OK

Table 176. DATA transfer (33 bits)

Name
WDATA or
Write or Read data
RDATA
Parity
Single parity of the 32 data bits
RM0367 Rev 7
Description
Description
Description
®
-M0+).
RM0367
®
one and is set to
®
-M0+ TRM and the