ST STM32G4 Series Reference Manual page 1710

Low-power universal asynchronous receiver transmitter (LPUART)
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in
details, refer
This bitfield can only be written when the LPUART is disabled (UE=0).
Bits 20:16 DEDT[4:0]: Driver Enable deassertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal.It is expressed in
lpuart_ker_ck
control and RS485 Driver
If the LPUART_TDR register is written during the DEDT time, the new data is transmitted
only when the DEDT and DEAT times have both elapsed.
This bitfield can only be written when the LPUART is disabled (UE=0).
Bit 15 Reserved, must be kept at reset value.
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register.
Bit 13 MME: Mute mode enable
This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch
between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between Mute mode and active mode.
Bit 12 M0: Word length
This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or
cleared by software (refer to bit 28 (M1) description).
This bit can only be written when the LPUART is disabled (UE=0).
Bit 11 WAKE: Receiver wakeup method
This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bitfield can only be written when the LPUART is disabled (UE=0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bitfield can only be written when the LPUART is disabled (UE=0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
This bitfield can only be written when the LPUART is disabled (UE=0).
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Section 37.5.20: RS232 Hardware flow control and RS485 Driver
clock cycles. For more details, refer
Enable.
RM0440 Rev 4
lpuart_ker_ck
clock cycles. For more
Section 38.4.13: RS232 Hardware flow
RM0440
Enable.