Digital Control Block Diagram - Agilent Technologies 8719ET Service Manual

DIGITAL CONTROL GROUP BLOCK DIAGRAM
8719/20/22ET/ES
TEST SET - I/0
INTERFACE
EXT BIAS
EXT REF
AUX INPUT
EXT TRIG
EXT AM
TEST SEQ
LIMIT TEST
MEAS RESTART
MINI-DIN KYBD
INTERCONNECT
A7 CPU
MINI-DIN KYBD PORT
INTERFACE
DIGITAL SIGNAL
PROCESSOR
ROM RAM
ADC
REG
sb529e
MEASURE
RESTART
A16 REAR PANEL
A1 FRONT PANEL
TEST SET - I/0
INTERFACE
TO A17
LEDS
TO A12
TO A10
KEYBOARD
TO A17
FROM A9
TO A17
PARALLEL GPIB
RS-232
INTERCONNECT
INTERCONNECT INTERCONNECT
RS-232 PORT PARALLEL PORT GPIB PORT
INTERFACE INTERFACE INTERFACE
EEPROM
MAIN CPU
FLASH RAM
MAIN RAM
RED LED
CONTROL/REFRESH
NORMAL= FLASHING
RPG
A2 FRONT PANEL PROCESSOR
FRONT
PANEL
PROCESSOR
+5 VD
FROM A17 A22 DISPLAY
MOTHERBOARD
INTERFACE
A3 DISK
VGA
INTERFACE
DRIVE
VGA
INTERCONNECT
TO A9
TO A10
TO A11
TO A12
TO A14
TO A51
EXT TRIG
A10 DIGITAL IF
TIMING
CONTROL
4 MHz FROM A12
ANALOG
BUS
1/2
SAMPLE
RATE IS
A OUT
16 kHz
IFA 4 kHz
B OUT
ADC
IFB 4 kHz
R OUT
IFR 4 kHz
v(1) v(2)
+0.37 V +2.5 V
A10 GND
A19 GSP A18 DISPLAY
CRYSTAL
DISPLAY
DIGITAL VIDEO
INTERFACE PALETTE
MEMORY
INVERTER ASSY
DIGITAL CONTROL GROUP BLOCK DIAGRAM
LSWP (FROM A14)
AUX
INPUT
v(3)
AUX IN
INSTRUMENT
NODES
TP20
A17
TP18
TP16
v(4)
TFT
LIQUID
(LCD)
XXX
LIGHT
CAUTION
1.5KV AC START UP
680V AC STEADY STA TE
A20
8719/20/22ET/ES