Agilent Technologies 8719ET Service Manual page 165

8719ET/8720ET OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 004
SOURCE
A26 HIGH STABILITY
FREQUENCY REFERENCE
(OPTION 1D5)
10 MHz
10 MHz ADJ
A59 SOURCE INTERFACE
W88
EXT
AM
LOW BAND ADJ
A11 PHASE LOCK
PLL FROM
10 MHz f(11) IF
SOURCE
PRECISION
1st IF 10 MHz
REFERENCE CONTROL
BOARD W2
PL REF
A12 REFERENCE
EXT
v(13)
REF IN
EXT REF
W40
POWER
A15 PREREGULATOR
SWITCHING
LINE POWER
POWER SUPPLY
AND
REGULATOR
GREEN LED
NORMAL= ON
sb511e
A14 FRACTIONAL-N (DIGITAL)
VCO
FN VCOTUNE
v(21)
4 N
SOURCE CONTROL SWITCHES FROM A9
LSWP
60 TO 240 MHz
CONTROL
LOWBAND
COUNT
AND
INPUTS
BIAS OSCILLATORS COUNTER v GATE
(23)
M/A/D/S
ALC
LO MED HI
OFFSET
SLOPE
BLANKING ADJ
FM YIG2
A68 6 dB
FM YIG1
ATTN
A55 YIG1
W82 A29
F=40 MHz
MAIN YIG2
+0.25/GHz
v(12) IF DET v (9)
10
PRETUNE MAIN YIG1
v(8) W7
SWPERR
1 MHz 2.55-20 GHz
W81
PRETUNE W6
DAC
RED LED AMBER LED
"UNLOCK" "PULL DOWN"
A53
MIXER/
AMP
f(17) PL REF
SRC TUNE
10 MHz
SET DAC # LOWBAND
W11
VCXO 1 MHz 4000 READ > 8 dBm
40 MHz
V(18)
4 MHz TO A10
A57
W8 3.8 GHz
VCXO
100 kHz TO A13
TUNE FIXED
40 MHz
16 kHz f(14) 100kHz
OSC
VCXO ADJ
v(15) VCO TUNE
f(16) 2nd LO 9.996 MHz
VCO 4
39.984 MHz
A8 POST-REGULATOR
A15W1
A16 REAR PANEL
+5VD
TEST SET-I/0 TEST SET-I/0
INTERFACE INTERFACE
+25V
EXT BIAS TO A17
+18V FAN POWER
EXT REF TO A12
REGULATORS
+8V AUX INPUT
MICROCIRCUIT POWER
TO A10
-8V EXT TRIG
INSTRUMENT POWER
-18V EXT AM TO A17
TEST SEQ
FROM A9
LIMIT TEST
MEAS RESTART TO A17
9 GREEN LEDS
RED LED
NORMAL= ON, STEADY
NORMAL= OFF
DIN KYBD RS-232
INTERCONNECT INTERCONNECT
A51 TEST SET
INTERFACE
A7 CPU
DIN KYBD PORT
RS-232 PORT
STEP INTERFACE INTERFACE
ATTENUATORS
CONTROL
TRANSFER SWITCH
AND
BIAS LOWER FT. PANEL
BIAS TO BIAS TEE'S
DIGITAL SIGNAL
PROCESSOR
ROM RAM
ADC
REG
RECEIVER
W9
A13 FRACTIONAL-N (ANALOG)
EXT TRIG
API s
100 kHZ
FROM A12 API ADJ
TO A10 TIMING
CONTROL
A52 PULSE
GENERATOR
STEP
RECOVERY
W31
DIODE
A58 M/A/D/S
ADC
J3
A20
J3 J1
W1
W3
J2
W42
SRC TUNE
0.05-2.55 GHz SET DAC # HIGH & MIDBAND
LOWBAND 3200-4095 READ > 0 dBm
SET DAC # LOWBAND
3750-4095 READ > -5 dBm
SRC TUNE
SET DAC # TO 4000
FOR HIGH, MID, & LOWBAND
J2 READS > -5 dBm
J3 READ > -19 dBm
LEGEND
MEASURE
RPG
RESTART
A2 FRONT PANEL PROCESSOR
A1 FRONT PANEL
A21
FRONT
KEYBOARD
PANEL
PROCESSOR
W83
PARALLEL GPIB
INTERCONNECT INTERCONNECT W99
A19 GSP
+5 VD
FROM A17 A22 DISPLAY
PARALLEL PORT GPIB PORT
INTERFACE INTERFACE MOTHERBOARD
INTERFACE
INTERFACE
EEPROM A3 DISK VGA
INTERFACE
DRIVE
MAIN CPU
W82
FLASH RAM
VGA
INTERCONNECT
MAIN RAM
RED LED
TO A9
NORMAL= FLASHING CONTROL/REFRESH
TO A10
TO A51
TO A12
TO A11
TO A14
CW 1 GHz
TEST PORT POWER -5 dBm
OPEN ON TEST PORT
10 MHz SINEWAVE 0.1V p-p
SMB TEE: A4, A5 OR A6
A9 SOURCE CONTROL BOARD
SOURCE
A10 DIGITAL IF
CONTROL
A4 2nd CONVERTER
LSWP (FROM A14)
SWITCHES TO
A59
AUX
4 MHz FROM A12
INPUT
v(3)
W47
AUX IN
ANALOG
BUS
INSTRUMENT
1/2
NODES
SAMPLE A6 2nd CONVERTER
TP18
RATE IS
A OUT A17
16 kHz
IFA 4 kHz
TP20
W48
B OUT
IFB 4 kHz
TP16
R OUT
IFR 4 kHz
PLL OUT TO
v(1) v(2) PHASE LOCK BD.
v(4)
+0.37V +2.5V A10 GND
W46
A5 2nd CONVERTER
W49
SIGNAL SEPARATION
STANDARD
W76
A69 STEP ATTN
DIGITAL BUS
This indicates Analog Bus node location. W32
f = Frequency Node
v = Voltage Node
OPTION 004
A18 DISPLAY
TFT
LIQUID
CRYSTAL
DISPLAY
DIGITAL VIDEO (LCD)
PALETTE
XXX
LIGHT
MEMORY
CAUTION
1.5KV AC START UP
680V AC STEADY STA TE
A20
INVERTER ASSY
8719ET/8720ET OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 004
W72
W74
SAMPLER A65 A SAMPLER
BIAS
F=30 MHz
S11
S12 J3 J2
S
W21
TRL
J1
CAL
A64 R1 SAMPLER
S11
A17 F=30 MHz
S21
J2
J3
S
W34
S12
S22
J1
REV
FWD
TRL A66 B SAMPLER
CAL
F=30 MHz
J2
J3
S
S21
S22 W23
J1
A62 DIRECTIONAL
COUPLER
W30
REFLECTION
A28 DC BLOCK
W78
A27 ATTN
W90
TRANSMISSION