Agilent Technologies 8719ET Service Manual page 166

8722ET OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 004
SOURCE
A26 HIGH STABILITY
FREQUENCY REFERENCE
(OPTION 1D5)
10 MHz
10 MHz ADJ
A59 SOURCE INTERFACE
W88
EXT
AM
LOW BAND ADJ
A11 PHASE LOCK
PLL FROM
10 MHz f(11) IF
SOURCE
PRECISION
CONTROL 1st IF 10 MHz
REFERENCE
W2
BOARD
PL REF
A12 REFERENCE
EXT
v(13)
REF IN
EXT REF
W40
POWER
A15 PREREGULATOR
SWITCHING
LINE POWER
POWER
SUPPLY
AND
REGULATOR
GREEN LED
NORMAL= ON
sb512e
A14 FRACTIONAL-N (DIGITAL)
VCO
4 N
SOURCE CONTROL SWITCHES FROM A9
LSWP
60 TO 240 MHz
CONTROL
LOWBAND
AND COUNT
OSCILLATORS INPUTS COUNTER GATE
BIAS v
(23)
M/A/D/S
ALC
LO MED HI
OFFSET
SLOPE
A54 YIG2
BLANKING ADJ
W79
W43
FM YIG2
20-40 GHz
FM YIG1 W80
A55 YIG1
A29
F=40 MHz MAIN YIG2
+0.25/GHz
v (9)
v(12) IF DET
10 W82 W1
PRETUNE MAIN YIG1
v(8) W7
1 MHz SWPERR
2.55-20 GHz
W81
W6
PRETUNE
RED LED DAC
AMBER LED
"UNLOCK" "PULL DOWN"
A53
MIXER/
AMP
f(17) PL REF
SRC TUNE
10 MHz
SET DAC # LOWBAND
W11
VCXO 1 MHz
4000 READ > 8 dBm
40 MHz
V(18) 4 MHz TO A10
W8 A57
VCXO 100 kHz TO A13
FIXED
TUNE 40 MHz 16 kHz f(14) 100kHz
OSC
3.8 GHz
VCXO ADJ
v(15) VCO TUNE
f(16) 2nd LO 9.996 MHz
VCO 4
39.984 MHz
A8 POST-REGULATOR
A15W1
A16 REAR PANEL
+5VD
TEST SET-I/0 TEST SET-I/0
INTERFACE INTERFACE
+25V
EXT BIAS
TO A17
+18V FAN POWER
EXT REF TO A12
REGULATORS
+8V MICROCIRCUIT POWER AUX INPUT
TO A10
-8V INSTRUMENT POWER EXT TRIG
-18V EXT AM TO A17
TEST SEQ
FROM A9
LIMIT TEST
MEAS RESTART TO A17
9 GREEN LEDS
RED LED
NORMAL= ON, STEADY
NORMAL= OFF
DIN KYBD RS-232
INTERCONNECT INTERCONNECT
A51 TEST SET
INTERFACE
A7 CPU
DIN KYBD PORT RS-232 PORT
STEP INTERFACE INTERFACE
ATTENUATORS
CONTROL
TRANSFER SWITCH
AND
BIAS LOWER FT. PANEL
BIAS TO BIAS TEE'S
DIGITAL SIGNAL
PROCESSOR
ROM RAM
ADC
REG
RECEIVER
W9
A13 FRACTIONAL-N (ANALOG)
EXT TRIG
API s
100 kHZ
FROM A12 API ADJ
TO A10 TIMING
CONTROL
A52 PULSE
GENERATOR
STEP
RECOVERY
W31
DIODE
A58 M/A/D/S
ADC
A25
J3 J3
A20
W5
J3
J1
W3
J2
W42
SRC TUNE
SET DAC # HIGH & MIDBAND
3200-4095 READ > 0 dBm
0.05-2.55 GHz
SET DAC # LOWBAND
LOWBAND
3750-4095 READ > -5 dBm
SRC TUNE
SET DAC # TO 4000
FOR HIGH, MID, & LOWBAND
J2 READS > -5 dBm
J3 READ > -19 dBm
LEGEND
MEASURE
RPG
RESTART
A2 FRONT PANEL PROCESSOR
A1 FRONT PANEL
A21
KEYBOARD
FRONT
PANEL
W83
PROCESSOR
PARALLEL GPIB
INTERCONNECT
INTERCONNECT W99
A19 GSP
+5 VD
PARALLEL PORT GPIB PORT A22 DISPLAY
FROM A17
INTERFACE INTERFACE
INTERFACE
INTERFACE
EEPROM A3 DISK VGA
DRIVE INTERFACE
MAIN CPU
FLASH RAM W82
VGA
MAIN RAM INTERCONNECT
TO A22
RED LED CONTROL/REFRESH
NORMAL= FLASHING
TO A9
TO A10
TO A51
TO A12
TO A11
TO A14
CW 1 GHz
TEST PORT POWER -5 dBm
OPEN ON TEST PORT
10 MHz SINEWAVE 0.1V p-p
SMB TEE: A4, A5 OR A6
SOURCE
A9 SOURCE CONTROL BOARD
CONTROL
A10 DIGITAL IF
SWITCHES TO
LSWP (FROM A14) A4 2nd CONVERTER
A59
AUX
4 MHz FROM A12
INPUT
v(3)
W47
AUX IN
ANALOG
BUS
INSTRUMENT
1/2
NODES
A6 2nd CONVERTER
SAMPLE
TP18
RATE IS
A OUT A17
16 kHz
IFA 4 kHz
TP20
W48
B OUT
IFB 4 kHz
TP16
R OUT
IFR 4 kHz
PLL OUT TO
PHASE LOCK BD.
v(1) v(2) v(4)
+0.37V
+2.5V A10 GND
W46
A5 2nd CONVERTER
W49
SIGNAL SEPARATION: STANDARD AND OPT 004
A69 STEP ATTN
DIGITAL BUS
W32
This indicates Analog Bus node location.
f = Frequency Node
v = Voltage Node
A18 DISPLAY
TFT
LIQUID
CRYSTAL
DISPLAY
DIGITAL VIDEO
(LCD)
PALETTE
XXX
LIGHT
MEMORY
CAUTION
1.5KV AC START UP
680V AC STEADY STA TE
A20
INVERTER ASSY
W72
SAMPLER
A65 A SAMPLER
BIAS
F=30 MHz
S11
S12 J3 J2
S
W74
W21
TRL
J1
CAL
A64 R1 SAMPLER
S11
A17 F=30 MHz
S21
J2
J3 S
S12
W34
S22
J1
REV
FWD
TRL A66 B SAMPLER
CAL
F=30 MHz
J2
J3
S
S21
S22 W23
J1
A62 DIRECTIONAL
COUPLER
W30
STANDARD
REFLECTION
W76
W78
A27 ATTN
W91
TRANSMISSION
OPTION 004
8722ET OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 004