Agilent Technologies 8719ET Service Manual page 161

8719ES/8720ES OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 007, 012, 085, 089, 1D5
SOURCE
A26 HIGH STABILITY
FREQUENCY REFERENCE
(OPTION 1D5)
10 MHz
10 MHz ADJ
A59 SOURCE INTERFACE
SOURCE CONTROL SWITCHES FROM A9
CONTROL
LOWBAND
AND
BIAS OSCILLATORS
M/A/D/S
ALC
LO MED HI
W88
OFFSET
EXT
AM
SLOPE
LOW BAND ADJ BLANKING ADJ
A11 PHASE LOCK
F=40 MHz
PLL FROM f(11) IF v(12) IF DET
10 MHz
SOURCE
PRECISION 10
1st IF 10 MHz
CONTROL
REFERENCE PRETUNE
W2 v(8)
BOARD
SWPERR
PL REF 1 MHz
RED LED AMBER LED
"UNLOCK" "PULL DOWN"
A12 REFERENCE
f(17) PL REF
EXT
10 MHz
v(13)
REF IN VCXO
EXT REF 40 MHz 1 MHz
V(18)
4 MHz TO A10
VCXO
W40
TUNE 16 kHz
40 MHz
W8
100 kHz TO A13
VCXO ADJ f(14) 100kHz
v(15) VCO TUNE
f(16) 2nd LO 9.996 MHz
VCO 4
39.984 MHz
POWER
A8 POST-REGULATOR
A15 PREREGULATOR A15W1
+5VD
+25V
SWITCHING
+18V FAN POWER
LINE POWER
REGULATORS
POWER
SUPPLY
+8V MICROCIRCUIT POWER
AND
REGULATOR -8V INSTRUMENT POWER
-18V
9 GREEN LEDS
GREEN LED RED LED
NORMAL= ON, STEADY
NORMAL= ON NORMAL= OFF
A51 TEST SET
INTERFACE
STEP
ATTENUATORS
CONTROL
TRANSFER SWITCH
AND
BIAS LOWER FT. PANEL
BIAS TO BIAS TEE'S
sb5106e
W9
A13 FRACTIONAL-N (ANALOG)
A14 FRACTIONAL-N (DIGITAL)
API s
VCO
4 N 100 kHZ
FROM A12 API ADJ
LSWP TO A10
60 TO 240 MHz
COUNT
INPUTS
COUNTER v GATE A52 PULSE
(23)
GENERATOR
STEP
RECOVERY
W31
DIODE
A58 M/A/D
FM YIG2
A68
FM YIG1
ATTN A20
A55 YIG1
W82 A29
+0.25/GHz MAIN YIG2
J3
v (9)
J1
W1
MAIN YIG1
W7 W3
2.55-20 GHz
W81
W6
PRETUNE
DAC
W42
A53
MIXER/
SRC TUNE
AMP 0.05-2.55 GHz SET DAC # HIGH & MIDBAND
LOWBAND
3200-4095 READ > 0 dBm
SET DAC # LOWBAND
SRC TUNE
3750-4095 READ > -5 dBm
SET DAC # LOWBAND W11
4000 READ > 8 dBm
A57
SRC TUNE
FIXED SET DAC # TO 4000
FOR HIGH, MID, & LOWBAND
OSC
J2 READS > -5 dBm
J3 READ > -19 dBm
3.8 GHz
MEASURE
RESTART
A16 REAR PANEL
A1 FRONT PANEL
TEST SET-I/0 TEST SET-I/0
INTERFACE INTERFACE
EXT BIAS TO A17 A21
EXT REF TO A12
KEYBOARD
AUX INPUT
TO A10
EXT TRIG
EXT AM
TO A17
TEST SEQ
FROM A9
LIMIT TEST
MEAS RESTART TO A17
DIN KYBD RS-232 PARALLEL GPIB
INTERCONNECT INTERCONNECT INTERCONNECT INTERCONNECT
A7 CPU
DIN KYBD PORT RS-232 PORT PARALLEL PORT GPIB PORT
INTERFACE
INTERFACE INTERFACE INTERFACE
EEPROM
MAIN CPU
DIGITAL SIGNAL
FLASH RAM
PROCESSOR
ROM RAM
MAIN RAM
ADC
REG
CONTROL/REFRESH
RECEIVER
EXT TRIG
A10 DIGITAL IF
TIMING
CONTROL
AUX
4 MHz FROM A12
INPUT
v(3)
ANALOG
BUS
1/2
SAMPLE
RATE IS TP18
A OUT
16 kHz
IFA 4 kHz
TP20
B OUT
ADC
IFB 4 kHz
TP16
R OUT
IFR 4 kHz
J3
v(1) v(2) v(4)
+0.37V +2.5V A10 GND
J2
W32
LEGEND
RPG DIGITAL BUS
A2 FRONT PANEL INTERFACE
This indicates Analog Bus node location.
f = Frequency Node
v = Voltage Node
FRONT
W83 PANEL
PROCESSOR
W99
A18 DISPLAY
A19 GSP
+5 VD
A22 DISPLAY
FROM A17
MOTHERBOARD
INTERFACE
DIGITAL VIDEO
INTERFACE PALETTE
A3 DISK
VGA
DRIVE INTERFACE
MEMORY
J2
W82
VGA
INVERTER ASSY
INTERCONNECT
TO A9
TO A10
TO A51
TO A12
TO A11
TO A14
CW 1 GHz
TEST PORT POWER -5 dBm
OPEN ON TEST PORT
10 MHz SINEWAVE 0.1V p-p
SMB TEE: A4, A5 OR A6
SOURCE A9 SOURCE CONTROL BOARD
CONTROL
SAMPLER
SWITCHES TO
BIAS
LSWP (FROM A14) A4 2nd CONVERTER
A59
S11
S12 J1 J3
J5
W21
W47 TRL
AUX IN
CAL
INSTRUMENT
NODES
A6 2nd CONVERTER S11
A17
S21
A17
J2
J6
S12
W34
W48
S22
J3
REV
PLL OUT TO
J7
PHASE LOCK BD.
FWD
W2
A5 2nd CONVERTER TRL
CAL
J8
J3
J4
S21
W49
S22
W23
OPT 007 CHANGES A74
TO A MECHANICAL TRANSFER
SWITCH
SIGNAL SEPARATION: STANDARD, OPT 007, 012
PORT 1
A74 SOLID STATE
TRANSFER SWITCH
A69 STEP
ATTN J2
W28
J1 A61 BIAS TEE
J3
0-55dB W29
A60 BIAS TEE
W27
A56 LOWER
S11/S21
FRONT
TO A51
PANEL
PORT 2
S12/S22
SIGNAL SEPARATION: OPT 085
PORT 1
SWITCH COUPLER
A74 MECHANICAL
A69 STEP TRANSFER SWITCH
W52
ATTN W61
OUT IN
J2
FROM
A58J2 J1
J3
W32 0-55dB W58 W52 W59
W60
TFT
LIQUID
CRYSTAL S11/S21
A56 LOWER
DISPLAY
FRONT TO A51 W52
(LCD)
PANEL SWITCH COUPLER
PORT 2
XXX S12/S22
LIGHT
CAUTION
1.5KV AC START UP
680V AC STEADY STA TE
A20
8719ES/8720ES OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 007, 012, 085, 089, 1D5
R1 LOOP: R1 LOOP: OPT 085, 089
STANDARD
TO A58J3
W23
W38
R
CHANNEL
OUT
A72
BUFFER
W52
AMP
A65 A SAMPLER
R
F=30 MHz
CHANNEL W50
J2 IN
S
OUT
A23
W33 SWITCH
J1
W54
A64 R1 SAMPLER A72 BUFFER
F=30 MHz
AMP
W51
J2
J3
S
W36 A24
SWITCH
J1
W18
IN
W20
TO A64J2
A66 B SAMPLER
F=30 MHz
J2
S
J1
OPT 012
OUT IN
A
A62 DIRECTIONAL
COUPLER
W17 W52 W16
J2
W30
J1
J3
PORT 1
STANDARD
W25
OPT 012
IN
OUT
B
A63 DIRECTIONAL
COUPLER
W14 W15
W52
W26 J2
W22
J1 J3 STANDARD
PORT 2
A62 DIRECTIONAL A70 STEP
COUPLER ATTN
A
OUT IN
J2
TO A65J2
W69 0-55dB
W17 W52 W65
J1
J3
PORT 1
W63
A63 DIRECTIONAL A71 STEP
COUPLER ATTN
OUT B IN
J2
TO A66J2
W62 W14 W52 W68 0-55dB W66
J1 J3
PORT 2
W52