Agilent Technologies 8719ET Service Manual page 162

8719ES/8720ES OVERALL BLOCK DIAGRAM FOR OPT 400, 012, 089, 1D5
SOURCE
A26 HIGH STABILITY
FREQUENCY REFERENCE
(OPTION 1D5)
10 MHz
10 MHz ADJ
A59 SOURCE INTERFACE
SOURCE CONTROL SWITCHES FROM A9
CONTROL
LOWBAND
AND
BIAS OSCILLATORS
M/A/D/S
W88
ALC
LO MED HI
EXT OFFSET
AM
SLOPE
LOW BAND ADJ BLANKING ADJ
A11 PHASE LOCK
F=40 MHz
10 MHz PLL FROM f(11) IF v(12) IF DET
SOURCE 10
PRECISION
1st IF 10 MHz
CONTROL
REFERENCE
BOARD W2
SWPERR
PL REF 1 MHz
RED LED AMBER LED
"UNLOCK" "PULL DOWN"
A12 REFERENCE
f(17) PL REF
EXT
10 MHz
v(13)
REF IN VCXO
EXT REF 40 MHz 1 MHz
V(18)
VCXO
W40
TUNE 16 kHz
40 MHz
VCXO ADJ
VCO 4
39.984 MHz
POWER
A8 POST-REGULATOR
A15 PREREGULATOR A15W1
+5VD
+25V
SWITCHING
+18V
LINE POWER
POWER SUPPLY
+8V
AND
REGULATOR -8V
-18V
9 GREEN LEDS
GREEN LED RED LED
NORMAL= ON, STEADY
NORMAL= ON NORMAL= OFF
A51 TEST SET
INTERFACE
CONTROL
AND
BIAS
sb5107e
W9
A13 FRACTIONAL-N (ANALOG)
A14 FRACTIONAL-N (DIGITAL)
VCO
4 N 100 kHZ
FROM A12
LSWP TO A10
60 TO 240 MHz
COUNT
INPUTS
COUNTER v GATE A52 PULSE
(23)
GENERATOR
STEP
RECOVERY
W31 DIODE
FM YIG2
A68
FM YIG1
ATTN A20
A55 YIG1 A29
W82
+0.25/GHz MAIN YIG2
J3
v (9)
W1
MAIN YIG1
PRETUNE W7
v(8)
2.55-20 GHz
W81
W6
PRETUNE
DAC
W42
A53
MIXER/
AMP 0.05-2.55 GHz
LOWBAND
SRC TUNE
SET DAC # LOWBAND
W11
4000 READ > 8 dBm
4 MHz TO A10
A57
FIXED
W8
OSC
100 kHz TO A13
3.8 GHz
f(14) 100kHz
v(15) VCO TUNE
f(16) 2nd LO 9.996 MHz
A16 REAR PANEL
A1 FRONT PANEL
TEST SET-I/0 TEST SET-I/0
INTERFACE INTERFACE
EXT BIAS TO A17 A21
FAN POWER
EXT REF TO A12
REGULATORS KEYBOARD
AUX INPUT
MICROCIRCUIT POWER
TO A10
EXT TRIG
INSTRUMENT POWER
EXT AM
TO A17
TEST SEQ
FROM A9
LIMIT TEST
MEAS RESTART TO A17
DIN KYBD RS-232 PARALLEL GPIB
INTERCONNECT INTERCONNECT INTERCONNECT INTERCONNECT
A7 CPU
DIN KYBD PORT RS-232 PORT PARALLEL PORT GPIB PORT
INTERFACE
STEP INTERFACE INTERFACE INTERFACE
ATTENUATORS
TRANSFER SWITCH
EEPROM
LOWER FT. PANEL
BIAS TO BIAS TEE'S
MAIN CPU
DIGITAL SIGNAL
FLASH RAM
PROCESSOR
ROM RAM
MAIN RAM
ADC
CONTROL/REFRESH
RED LED
REG
NORMAL= FLASHING
RECEIVER
EXT TRIG
API s
A10 DIGITAL IF
API ADJ
TIMING
CONTROL
4 MHz FROM A12
1/2
SAMPLE
RATE IS
A OUT
16 kHz
B OUT
A58 M/A/D ADC
R OUT
v(1) v(2)
+0.37V +2.5V
J1
J2
W3
SRC TUNE
SET DAC # HIGH & MIDBAND
3200-4095 READ > 0 dBm
SET DAC # LOWBAND
3750-4095 READ > -5 dBm
W32
LEGEND
MEASURE
RPG DIGITAL BUS
RESTART
A2 FRONT PANEL INTERFACE
This indicates Analog Bus node location.
f = Frequency Node
v = Voltage Node
FRONT
W83 PANEL
PROCESSOR
W99
A19 GSP
+5 VD
A22 DISPLAY
FROM A17
INTERFACE
DIGITAL VIDEO
INTERFACE PALETTE
A3 DISK
VGA
DRIVE INTERFACE
MEMORY
J2
W82
VGA
TO A22
INTERCONNECT
TO A9
TO A10
TO A51
TO A12
TO A11
TO A14
CW 1 GHz
TEST PORT POWER -5 dBm
OPEN ON TEST PORT
10 MHz SINEWAVE 0.1V p-p
SMB TEE: A4, A5 OR A6
A9 SOURCE CONTROL BOARD
SOURCE
CONTROL
A4 2nd CONVERTER
LSWP (FROM A14)
SWITCHES TO
S11
A59
AUX S12 J1
J5
INPUT
v(3)
W47 TRL
AUX IN
ANALOG
CAL
BUS
INSTRUMENT
NODES
A6 2nd CONVERTER S11
A17
TP18 S21
A17
J2
J6
IFA 4 kHz
S12
TP20 W48
S22
IFB 4 kHz
TP16
IFR 4 kHz
J3
J7
PLL OUT TO
v(4)
PHASE LOCK BD.
A10 GND FWD
W2
A5 2nd CONNVERTER TRL
CAL
J8
J4
S21
W49
S22
SIGNAL SEPARATION: OPT 400, 012
J2
W39
A74 SWITCH A70 STEP
SPLITTER ATTN
J3
0-55dB
W38
J1 J4 A61 BIAS TEE
W41 A71 STEP
A60 BIAS TEE
ATTN
J5
W40 0-55dB W37
A56 LOWER S11/S21
TO A51
FRONT
PANEL
S12/S22
R1 LOOP: OPT 400, 089
NON-OPT 089
OUT
W55 W52
A18 DISPLAY
TFT OPT 089
LIQUID
CRYSTAL TO A74J3
DISPLAY
(LCD)
W56
XXX
LIGHT
A72 BUFFER
AMP
CAUTION
1.5KV AC START UP
680V AC STEADY STA TE
A20
INVERTER ASSY
SAMPLER A65 A SAMPLER
BIAS
F=30 MHz
J3 J2
S
W21
J1
A64 R1 SAMPLER
F=30 MHz
J2
J3
S
W34
J1
A67 R2 SAMPLER A73 BUFFER
F=30 MHz
AMP
J2
J3 S
W35
W77
J1
A66 B SAMPLER
F=30 MHz
J3 J2
S
W23
J1
OPT 012
OUT IN
A
A62 DIRECTIONAL
PORT 1
COUPLER
W17 W52 W16
J2
W30
J1 J3 NON-OPT 012
PORT 1
W25
OPT 012
IN
OUT
B
A63 DIRECTIONAL
COUPLER
W14 W15
W52
W26 J2
W22
J1 J3 NON-OPT 012
PORT 2
PORT 2
A72 BUFFER
IN
AMP
W33 W36
OUT IN
TO A64J2
W52
W18
W54
A23
A24
SWITCH
SWITCH
W50 W57 W53
8719ES/8720ES OVERALL BLOCK DIAGRAM FOR OPT 400, 012, 089, 1D5