Agilent Technologies 8719ET Service Manual page 163

8722ES OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 007, 012, 085, 089, 1D5
SOURCE
A26 HIGH STABILITY
FREQUENCY REFERENCE
(OPTION 1D5)
10 MHz
10 MHz ADJ
A59 SOURCE INTERFACE
SOURCE CONTROL SWITCHES FROM A9
CONTROL
LOWBAND
AND
BIAS OSCILLATORS
M/A/D/S
W88
ALC
LO MED HI
EXT OFFSET
AM
SLOPE
LOW BAND ADJ BLANKING ADJ
A11 PHASE LOCK
F=40 MHz
W2
PLL FROM f(11) IF v(12) IF DET
10 MHz
SOURCE 10
PRECISION
1st IF 10 MHz
CONTROL
REFERENCE PRETUNE
BOARD v(8)
SWPERR
PL REF 1 MHz
RED LED AMBER LED
"UNLOCK"
"PULL DOWN"
A12 REFERENCE
f(17) PL REF
EXT 10 MHz
REF IN v(13) VCXO
EXT REF 1 MHz
V(18) 40 MHz
4 MHz TO A10
VCXO
W40
TUNE 16 kHz
40 MHz
100 kHz TO A13
VCXO ADJ f(14) 100kHz
v(15) VCO TUNE
f(16) 2nd LO 9.996 MHz
VCO
4
39.984 MHz
POWER
A15 PREREGULATOR A8 POST-REGULATOR
A15W1
+5VD
+25V
SWITCHING
LINE +18V
POWER
POWER REGULATORS
SUPPLY +8V
AND
-8V
REGULATOR
-18V
9 GREEN LEDS
GREEN LED RED LED
NORMAL= ON, STEADY
NORMAL= ON NORMAL= OFF
A51 TEST SET
INTERFACE
CONTROL
AND
BIAS
sb58e
W9
A13 FRACTIONAL-N (ANALOG)
A14 FRACTIONAL-N (DIGITAL)
API s
VCO
4 N 100 kHZ
FROM A12 API ADJ
LSWP TO A10
60 TO 240 MHz
COUNT
INPUTS
COUNTER v GATE
A52 PULSE
(23)
GENERATOR
STEP
RECOVERY
W31 DIODE
A54 YIG2
W79
W43
FM YIG2
20-40 GHz A25
FM YIG1 J3
A20
A55 YIG1
W82
A29
+0.25/GHz
MAIN YIG2
J3
v (9)
W80 W1
MAIN YIG1
W7
W3 W5
2.55-20 GHz
W81
W6
PRETUNE
DAC
W42
A53
SRC TUNE
MIXER/
SET DAC # HIGH & MIDBAND
0.05-2.55 GHz
AMP 3200-4095 READ > 0 dBm
LOWBAND
SET DAC # LOWBAND
3750-4095 READ > -5 dBm
SRC TUNE
SET DAC # LOWBAND W11
4000 READ > 8 dBm
A57
SRC TUNE
FIXED SET DAC # TO 4000
W8
FOR HIGH, MID, & LOWBAND
OSC
J2 READS > -5 dBm
J3 READ > -19 dBm
3.8 GHz
MEASURE
RESTART
A16 REAR PANEL
A1 FRONT PANEL
TEST SET-I/0 TEST SET-I/0
INTERFACE INTERFACE
EXT BIAS
TO A17
A21
FAN POWER
EXT REF TO A12
KEYBOARD
MICROCIRCUIT POWER AUX INPUT
TO A10
INSTRUMENT POWER EXT TRIG
EXT AM TO A17
TEST SEQ
FROM A9
LIMIT TEST
MEAS RESTART TO A17
DIN KYBD RS-232 PARALLEL GPIB
INTERCONNECT
INTERCONNECT INTERCONNECT INTERCONNECT
A7 CPU
DIN KYBD PORT RS-232 PORT PARALLEL PORT GPIB PORT
STEP INTERFACE INTERFACE INTERFACE INTERFACE
ATTENUATORS
TRANSFER SWITCH
LOWER FT. PANEL EEPROM
BIAS TO BIAS TEE'S
MAIN CPU
DIGITAL SIGNAL
ROM RAM
PROCESSOR
ROM RAM
MAIN RAM
ADC
REG
CONTROL/REFRESH
RECEIVER
EXT TRIG
A10 DIGITAL IF
LSWP (FROM A14)
TIMING
CONTROL
AUX
4 MHz FROM A12
INPUT
v(3)
ANALOG
BUS
1/2
SAMPLE
TP18
RATE IS
A OUT
16 kHz
IFA 4 kHz
TP20
A58 M/A/D B OUT
ADC
IFB 4 kHz
TP16
R OUT
IFR 4 kHz
v(1)
J3 v(2) v(4)
+0.37V A10 GND
+2.5V
J1
J2
W32
LEGEND
RPG DIGITAL BUS
A2 FRONT PANEL PROCESSOR
This indicates Analog Bus node location.
f = Frequency Node
v = Voltage Node
FRONT
PANEL
W83 W83
PROCESSOR
W99
A19 GSP A18 DISPLAY
+5 VD
FROM A17 A22 DISPLAY
LIQUID
MOTHERBOARD
INTERFACE CRYSTAL
DISPLAY
DIGITAL VIDEO
(LCD)
INTERFACE PALETTE
A3 DISK VGA
DRIVE INTERFACE
LIGHT
MEMORY
J2
W82
INVERTER ASSY
VGA
INTERCONNECT
TO A9
TO A10
TO A51
TO A12
TO A11
TO A14
CW 1 GHz
TEST PORT POWER -5 dBm
OPEN ON TEST PORT
10 MHz SINEWAVE 0.1V p-p
SMB TEE: A4, A5 OR A6
SOURCE A9 SOURCE CONTROL BOARD
CONTROL
A65 A SAMPLER
SAMPLER
SWITCHES TO
A4 2nd CONVERTER BIAS
A59 F=30 MHz
S11
J1 J3
S12
J5
W21
W47 TRL
AUX IN
CAL
INSTRUMENT
A64 R1 SAMPLER
NODES
A6 2nd CONVERTER
S11
F=30 MHz
S21
A17
J2
J3
J6
S12 W34
W48
S22
J3
REV
PLL OUT TO J7
PHASE LOCK BD.
FWD
W2
A5 2nd CONNVERTER
TRL A66 B SAMPLER
CAL
F=30 MHz
J8
J4
J3
S21
W49
S22 W23
OPT 007 CHANGES A74
TO A MECHANICAL TRANSFER
SWITCH
SIGNAL SEPARATION: STANDARD, OPT 007, 012
PORT 1
A74 SOLID STATE
A69 STEP TRANSFER SWITCH
ATTN
J2
W28 W25
J1 A61 BIAS TEE
0-55dB W29 J3
A60 BIAS TEE
W27 W26
A56 LOWER
S11/S21
FRONT
TO A51
PANEL
PORT 2
S12/S22
SIGNAL SEPARATION: OPT 085
PORT 1
SWITCH COUPLER
A74 MECHANICAL
TRANSFER
A69 STEP
SWITCH
W52
ATTN W61
OUT IN
J2
FROM
J1
A58J2
J3
W32 0-55dB W58 W52 W59
W60
TFT
A56 LOWER S11/S21
FRONT TO A51
W52
PANEL SWITCH COUPLER
PORT 2
XXX
S12/S22
CAUTION
1.5KV AC START UP
680V AC STEADY STA TE
A20
8722ES OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 007, 012, 085, 089, 1D5
R1 LOOP:
R1 LOOP: OPT 085, 089
W23
STANDARD
R CHANNEL TO A58
OUT
J3
W38
A75
W52
ATTN
R CHANNEL
IN
A72
BUFFER
W33
AMP
J2
S
W50
J1
OUT
A23
A72 BUFFER
A75 ATTN
SWITCH
AMP
W54
J2
S
W36 W51 W52
J1
A24
SWITCH
W18
IN
W20
TO A64
J2
J2
S
J1
OPT 012
OUT
IN
A
A62 DIRECTIONAL
COUPLER
W17 W52 W16
J2
W30
J1 J3
PORT 1 STANDARD
OPT 012
OUT IN
B
A63 DIRECTIONAL
COUPLER *
W14 W52 W15
J2
W22
J1 J3 STANDARD
PORT 2
A62 DIRECTIONAL
A70 STEP
COUPLER ATTN
OUT IN
A
J2
TO A65J2
0-55dB W65
W17 W52 W69
J1 J3
PORT 1
W63
A71 STEP
A63 DIRECTIONAL
ATTN
COUPLER IN
OUT B
J2
TO A66J2
0-55dB
W62 W14 W52 W68 W66
J1 J3
PORT 2