Interrupt Processing - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.4.2

Interrupt Processing

The interrupt controller transmits the interrupt level to the CPU when an interrupt
request is generated by a peripheral function. If the CPU is able to receive the
interrupt, the CPU temporarily halts the currently executing program and executes the
interrupt processing routine.
Interrupt Processing
The procedure for interrupt operation is performed in the following order: interrupt source
generated at peripheral function, set the interrupt request flag bit (request FF), discriminate the
interrupt request enable bit (enable FF), the interrupt level (ILR1, 2, 3 and CCR: IL1, IL0), and
then simultaneously generated interrupt requests with the same level, and then check the
interrupt enable flag (CCR: I).
Figure 3.4-2 shows the interrupt processing.
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