Operation Of Port 3 - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 4 I/O PORTS
4.5.2

Operation of Port 3

This section describes the operations of the port 3.
Operation of Port 3
Operation as an output port
• Setting the corresponding DDR3 register bit to "1" sets a pin as an output port.
• When a pin is set as an output port, the output buffer is "ON" and the pin outputs the data
stored in the output latch.
• Writing data to the PDR3 register stores the data in the output latch and outputs the data to
the pin via the output buffer.
• Reading the PDR3 register returns the pin value.
Operation as an input port
• Setting the corresponding DDR3 register bit to "0" sets a pin as an input port.
• When a pin is set as an input port, the output buffer is "OFF" and the pin goes to the high-
impedance state.
• Writing data to the PDR3 register stores the data in the output latch but does not output the
data to the pin.
• Reading the PDR3 register returns the pin value.
Operation as a peripheral output
• Set the output enable bit of the peripheral to "enable" to use a pin as a peripheral output.
• As the pin value can be read by the PDR3 register even if the peripheral output is enabled,
the peripheral output value can be read.
Operation as a peripheral input
• Set to "0" the DDR3 register bit corresponding to the input pin of the peripheral to set the
port as an input.
• The pin value is continuously input for ports that also serve as a pin with a peripheral input.
• Reading the PDR3 register returns the pin value regardless of whether or not the peripheral
is using the input pin.
Operation at reset
• Resetting the CPU initializes the DDR3 register values to "0". This sets all output buffers
"OFF" (all pins become input ports) and sets the pins to the high-impedance state.
• The PDR3 register is not initialized by a reset. Therefore, to use as output ports, the output
data must be set in the PDR3 register before setting the corresponding DDR3 register bits to
output mode.
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