Fujitsu F2MC-8L Series Hardware Manual page 327

CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT
Table 14.3-1 Functions of Peripheral Control Clock Register (SCGC) Bits (Continued)
Bit name
Bit 1 SCG1, SCG0: Clock
Bit 0 select bits
300
• These bits select the peripheral control clock output and enable
or disable clock output.
• When these bits are not "00
the peripheral control clock output pin (SCO) to output a square
wave at the selected frequency.
• The peripheral control clock output frequency can be selected
from among subclock and main clock frequency-divided outputs
(two types).
• When these bits are "00
EC/SCO pin serves as a general-purpose port pin (P33) or the
external clock input pin (EC) for the 8/16-bit timer/counter.
Note:
Peripheral control clock output is stopped by transition to main-
stop or subclock mode with the main clock frequency-divided
output selected (SCG1, SCG0 = "10
to sub-stop mode with the subclock frequency-divided output
selected (SCG1, SCG0 = "01
Tip:
Even when the device enters main-stop mode, the peripheral
control clock can be output by selecting the subclock frequency-
divided output and setting the pin state specification bit (STBC:
SPL) to "0".
Function
", the P33/EC/SCO pin serves as
B
", clock output is disabled and the P33/
B
" or "11 ") or by transition
B B
").
B