Figure B.2-3 Mulu A; Figure B.2-4 Divu A - Fujitsu F2MC-8L Series Hardware Manual

APPENDIX B Overview of Instructions
MULU A
This instruction performs an unsigned multiplication of AL (lower 8 bits of the accumulator) and
TL (lower 8 bits of the temporary accumulator) and stores the 16-bit result in A. The content of T
(temporary accumulator) does not change. The arithmetic operation does not use the pre-
execution contents of AH (upper 8 bits of the accumulator) and TH (upper 8 bits of the
temporary accumulator). Since the flags remain unchanged, use care when branching is
required based on the result of multiplication.
Figure B.2-3 shows an outline of the instruction operation.
DIVU A
This instruction divides the 16 bits of T by the 8 bits of AL, treating the data as unsigned. The
instruction stores the result in AL and the remainder in TL, both as 8 bit data. AH and TH are
both set to "zero". The arithmetic operation does not use the value of AH prior to instruction
execution. The result is not assured for data that produces a result that exceeds 8 bits. As there
is no indication that the result exceeded 8 bits, check the data before performing. Since the
flags remain unchanged, be careful when branching is required based on the result of the
division.
Figure B.2-4 shows an outline of the instruction operation.
XCHW A, PC
This instruction exchanges the contents of A and PC, and as a result branches to the address
corresponding to contents of A before execution. The contents of A after execution assume the
address next to the address where the operation code of the "XCHW A,PC" is stored. The
instruction can be used to specify a table in the main routine which is used in a subroutine.
314

Figure B.2-3 MULU A

(Before execution)
5678
H
A
1234
H
T

Figure B.2-4 DIVU A

(Before execution)
5678
A H
1862
T H
(After execution)
1860
H
A
1234
H
T
(After execution)
0034
A H
0002
T H