Figure 7.7-3 Operation Of Counter Functions In 16-Bit Mode - Fujitsu F2MC-8L Series Hardware Manual

Figure 7.7-3 illustrates operations of the counter function in 16-bit mode.

Figure 7.7-3 Operation of Counter Functions in 16-bit Mode

External clock
Counter cleared
T1STR bit
(T1STP = "0")
Counter value 0000
Comparate data
latch 1
(Lower 8 bits of
compared value)
Comparate data
latch 2
(Upper 8 bits of
compared value)
Load
T1DR register*
(Lower 8 bits of
set value)
T2DR register*
(Upper 8 bits of
set value)
T1IF register
*: Each register can be set to any value at an arbitrary timing. Upon activation of the counter and detection of a match,
the data register value is loaded to the comparate data latch. The counter is cleared at this time.
Check:
Verify the validity of the values by reading them twice before reading the counter values in
opration in 16-bit mode.
0001 0002 0003
H H H H
88
H
13
H
Set data (1234
7.7 Operation of Counter Function
88
H
13
H
34
H
12
H
)
H
1388 0000 0001
H H H
34
H
12
H
Load
Cleared by program
181