Fujitsu F2MC-8L Series Hardware Manual page 19

FIGURES
Figure 1.4-1 MB89120/120A Series Block Diagram ....................................................................................... 8
Figure 1.5-1 FTP-48P-M13 Pin Assignment ................................................................................................... 9
Figure 1.5-2 DIP-48P-M01 Pin Assignment .................................................................................................. 10
Figure 1.5-3 MQP-48C-P01 Pin Assignment ................................................................................................ 11
Figure 1.6-1 FPT-48P-M13 Package Dimensions ........................................................................................ 12
Figure 1.6-2 DIP-48P-M01 Package Dimensions ......................................................................................... 13
Figure 1.6-3 MQP-48C-P01 Package Dimensions ....................................................................................... 14
Figure 3.1-1 Memory Map ............................................................................................................................. 27
Figure 3.1-2 Allocation 16-bit Data in Memory .............................................................................................. 30
Figure 3.1-3 Allocation of 16-bit Data in an Instruction ................................................................................. 30
Figure 3.2-1 Dedicated Register Configuration ............................................................................................. 32
Figure 3.2-2 Structure of Condition Code Register ....................................................................................... 34
Figure 3.2-3 Change of Carry Flag by Shift Instruction ................................................................................. 35
Figure 3.2-4 Structure of Register Bank Pointer ........................................................................................... 37
Figure 3.2-5 Rule for Conversion of Actual Addresses of General-purpose Register Area .......................... 37
Figure 3.3-1 Register Bank Structure ............................................................................................................ 38
Figure 3.4-1 Structure of Interrupt Level Setting Registers ........................................................................... 42
Figure 3.4-2 Interrupt Processing .................................................................................................................. 45
Figure 3.4-3 Example of Multiple Interrupts .................................................................................................. 47
Figure 3.4-4 Interrupt Processing Time ......................................................................................................... 49
Figure 3.4-5 Stack Operation at Start of Interrupt Processing ...................................................................... 51
Figure 3.4-6 Stack Area for Interrupt Processing .......................................................................................... 52
Figure 3.5-1 Block Diagram of External Reset Pin ........................................................................................ 55
Figure 3.5-2 Reset Operation Flowchart ....................................................................................................... 56
Figure 3.6-1 Clock Supply Map ..................................................................................................................... 60
Figure 3.6-2 Connection Example for Crystal or Ceramic Resonator ........................................................... 61
Figure 3.6-3 Connection Example for External Clock ................................................................................... 62
Figure 3.6-4 Block Diagram of Clock Controller ............................................................................................ 63
Figure 3.6-5 System Clock Control Register (SYCC) ................................................................................... 65
Figure 3.6-6 Operation of an Oscillator after Starting Oscillation .................................................................. 71
Figure 3.7-1 Standby Control Register (STBC) ............................................................................................. 81
Figure 3.7-2 State Transition Diagram 1 (Product with Power-on Reset Function in
Dual-clock Configuration) ......................................................................................................... 83
Figure 3.7-3 State Transition Diagram 2 (Product without Power-on Reset Function in
Dual-clock Configuration) ......................................................................................................... 86
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