Figure 12.5-2 Watch Prescaler Operation - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 12 WATCH PRESCALER
Counter value
7FFF
H
0000
H
Subclock oscillation
stabilization delay
time
Power-on reset
(optional)
WIF bit
WIE bit
SLP bit
(STBC register)
STP bit
(STBC register)
This assumes that the interrupt interval time select bits (WS1 and WS0) in the watch prescaler control register (WPCR)
are set to "11" (at 2
270

Figure 12.5-2 Watch Prescaler Operation

Interval cycle
Cleared by interrupt handler
Sub-sleep
Wake-up from sleep
mode by IRQ7
15
/F ).
CL
Cleared for transition to
sub-stop mode
Subclock oscillation
stabilization delay
time
Sub-stop
Wake-up from stop mode by external interrupt
Counter cleared
" "
(WPCR: WCLR = 0 )