Structure Of Timebase Timer; Figure 5.2-1 Block Diagram Of Timebase Timer - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 5 TIMEBASE TIMER
5.2

Structure of Timebase Timer

The timebase timer consists of the following four blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
Block Diagram of Timebase Timer
Timebase
timer counter
Divide-by
2 1 2
-two F
CH
Counter Clear
Watchdog
timer clear
Power-on reset
Sub-clock mode start
Stop mode start
(in main clock mode)
IRQ6
timebase timer
interrupt
OF: Overflow
F : Main clock source oscillation
CH
Timebase timer counter
A 21-bit up-counter that uses the divide-by-two main clock source oscillation as a count clock.
This counter stops operation when the main clock stops oscillation.
Counter clear circuit
In addition to being cleared by setting the TBTC register (TBR = "0"), the counter is cleared
when the device changes to stop mode (STBC: STP = "1") and by power-on reset (optional).
Interval timer selector
Selects one of four operating timebase timer counter bits as the interval timer bit. An overflow
on the selected bit triggers an interrupt.
134

Figure 5.2-1 Block Diagram of Timebase Timer

2 2 3 ... 2 6 2 7
Counter
clear circuit
2 8 2 9 2 10 2 11 2 12
OF
OF
OF
Interval
timer selector
TBOF TBIE
Timebase timer control register (TBTC)
To watchdog timer
To buzzer output
2 13 2 14 2 15 2 16
Clock controller
oscillation stabilization
delay time selecter
OF
TBC1 TBC0
2 17 . . . 2 21
TBR