Operation Of Port 1 - Fujitsu F2MC-8L Series Hardware Manual

4.3.2

Operation of Port 1

This section describes the operations of port 1.
Operation of Port 1
Operation as an output port
• Setting the DDR1 register bit corresponding to a port 1 pin to "1" sets the pin as an output
port pin.
• When a pin is set as an output port pin, the output buffer is "ON" and the data in the output
latch is output to the pin.
• Writing data to the PDR1 register stores the data in the output latch and outputs the data to
the pin through the output buffer.
• Reading the PDR1 register returns the pin value.
Operation as an input port
• Setting the DDR1 register bit corresponding to a port 1 pin to "0" sets the pin as an input port
pin.
• When a pin is set as an input port pin, the output buffer is "OFF" and the pin enters a high
impedance state.
• Writing data to the PDR1 register stores the data in the output latch but does not output the
data to the pin.
• Reading the PDR1 register returns the pin value.
Operation at reset
• Resetting the CPU initializes the DDR1 register value to "0". This sets all output buffers to
"OFF" (all pins become input port pins) and sets the pins to the high impedance state.
• The PDR1 register is not initialized at a reset. To use a port 1 pin as an output port pin,
therefore, set output data in the PDR1 register and then set the corresponding bit in the
DDR1 register to serve for output.
Operation in stop or watch mode
A port 1 pin enters a high impedance state if the pin state specification bit (SPL) in the standby
control register (STBC) is "1" when the device changes to stop or watch mode. This is because
the output buffer is forced to become "OFF", regardless of the value in the DDR1 register. Note
that the input is fixed to prevent leakage by opening the input.
4.3 Port 1
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