Fujitsu F2MC-8L Series Hardware Manual page 114

Switching to and from clock mode (not in standby mode)
Table 3.7-5 Switching to and from Clock Mode (Product without Power-on Reset Function in Dual-clock
Configuration)
State transition
Transition to normal (main-
RUN) state in main clock
mode after power-on reset
Reset in main-RUN state
Transition from main-RUN
state to sub-RUN state
Wake-up from sub-RUN
state to main-RUN state
Reset in sub-RUN state
SYCC:
*:
[1] External reset input is required until oscillation of the main clock
becomes stable.
[2] Reset input canceled
[3] External reset, software reset, or watchdog reset
[4] SYCC: SCS = "0"*
[5] SYCC: SCS = "1"
[6] End of main clock oscillation stabilization delay time (This can be
checked with the SCM bit in tne SYCC register.)
[7] Software reset or watchdog reset
[8] External reset input is required until oscillation of the main clock
becomes stable.
[9] Software reset or watchdog reset
[10] External reset input is required until oscillation of the main clock
becomes stable.
System clock control register
Transition to the sub-RUN state immediately after turning the power on takes
place after the end of the subclock oscillation stabilization delay time.
3.7 Standby Modes (Low-power Consumption)
Transition conditions
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