Table 3.7-2 Standby Control Register (Stbc) Bits - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU

Table 3.7-2 Standby Control Register (STBC) Bits

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
82
Bit
• Sets the CPU changing to stop mode.
STP: • Writing "1" to this bit causes the CPU change to stop mode.
Stop bit • Writing "0" to this bit has no effect on operation.
• Reading this bit always returns "0".
• Sets the CPU changing to sleep mode.
SLP: • Writing "1" to this bit causes the CPU change to sleep mode.
Sleep bit • Writing "0" to this bit has no effect on operation.
• Reading this bit always returns "0".
• Specifies the states of the external pins during stop or watch
mode.
SPL: • Writing "0" to this bit specifies that external pins hold their
Pin state states (levels) on changing to stop or watch mode.
specification • Writing "1" to this bit specifies that external pins go to high-
bit impedance state on entering stop or watch mode. (Pins with
a pull-up resistor (optional) go to the "H" level.)
• Initialized to "0" by a reset.
• Specifies a software reset.
• Writing "0" to this bit generates an internal reset source for
four instruction cycles.
• Writing "1" to this bit has no effect on operation.
RST: • Reading this bit always returns "1".
Software reset Reference:
bit If a software reset takes place in subclock mode, the CPU
restarts operation in main clock mode after taking the
oscillation stabilization delay time. If the reset output enable
option is selected, therefore, the reset signal remains output
during the oscillation stabilization delay time.
• Specifies mode transition to watch mode.
• Writing to this bit is enabled only in subclock mode (SYCC:
TMD: SCS = "0").
Watch bit • Writing "1" to this bit causes the CPU to enter watch mode.
• Writing "0" to this bit has no effect on operation.
• Reading this bit always returns "0".
• The read value is indeterminate.
Unused bits
• Writing to these bits has no effect on operation.
Function