Table 4.5-4 Port 3 Pin State - Fujitsu F2MC-8L Series Hardware Manual

Operation in stop mode and watch mode
The pins go to the high-impedance state if the pin state specification bit in the standby control
register (STBC: SPL) is "1" when the device changes to stop or watch mode. This is achieved
by forcibly setting the output buffer to "OFF" regardless of the DDR3 register value. Note that
the pins P30 to P32 and P34 to P36 must be fixed externally to prevent leakage by opening the
inputs. P33 and P37 are internally fixed.
Table 4.5-4 lists the port 3 pin states.

Table 4.5-4 Port 3 Pin State

Pin name
P30/SCK to P37/BZ
SPL: Pin state specification bit in the standby control register (STBC)
Hi-z: High impedance
Tip:
Pins with a pull-up resistor (optional) go to the "H" level (pull-up state) rather than to the high-
impedance state when the output buffer is "OFF".
Normal operation
Main-sleep mode
Main-stop mode (SPL = 0)
Sub-sleep mode
Sub-stop mode(SPL = 0)
Watch mode (SPL = 0)
General-purpose I/O ports/peripheral I/O
Main-stop mode (SPL = 1)
Sub-stop mode (SPL = 1)
Watch mode (SPL = 1)
Hi-z
4.5 Port 3
Reset
Hi-z
123