Fujitsu F2MC-8L MB89120A Series Manuals

Manuals and User Guides for Fujitsu F2MC-8L MB89120A Series. We have 1 Fujitsu F2MC-8L MB89120A Series manual available for free PDF download: Hardware Manual

Fujitsu F2MC-8L MB89120A Series Hardware Manual

Fujitsu F2MC-8L MB89120A Series Hardware Manual (373 pages)

8-BIT MICROCONTROLLER

Brand: Fujitsu | Category: Microcontrollers | Size: 1.71 MB

Table of Contents

Table of Contents
14
Chapter 1 Overview

28
Chapter 2 Handling Devices

48
- Notes on Handling Devices
  49
Chapter 3 Cpu

52
Chapter 4 I/O Ports

124
- Overview of I/O Ports
  125
- Table 4.1-1 Port Function
  125
- Table 4.1-2 Port Registers
  126
- Port 0
  127
- Port 1
  134
- Port 2
  140
- Port 3
  144
- Port 4
  151
- Program Example for I/O Ports
  155
- Figure 4.7-1 Connection Example for an Eight-Segment LED
  155
Chapter 5 Timebase Timer

158
Chapter 6 Watchdog Timer

172
Chapter 7 8/16-Bit Timer/Counter

184
Chapter 8 8-Bit Serial I/O

220
Chapter 9 Buzzer Output

246
- Overview of Buzzer Output
  247
- Table 9.1-1 Output Frequency
  247
- Structure of Buzzer Output
  249
- Figure 9.2-1 Block Diagram of Buzzer Output
  249
- Buzzer Output Pin
  250
- Figure 9.3-1 Block Diagram of P37/BZ/(RCO) Pin
  250
- Buzzer Output Register
  251
- Program Example for Buzzer Output
  254
Chapter 10 External Interrupt Circuit 1 (Edge)

256
Chapter 11 External Interrupt Circuit 2 (Level)

272
Chapter 12 Watch Prescaler

288
Chapter 13 Remote-Control Transmission Frequency Generator

302
Chapter 14 Peripheral Control Clock Output

322
Appendix

330
- APPENDIX A I/O Map
  
  331
  - Table A-1 I/O Map
    331
- APPENDIX B Overview of Instructions
  
  334
  - Figure B-1 Instruction Code and Instruction Map
    334
  - Table B-1 Instruction List Symbols
    334
    
    Addressing
    336
    
    Figure B.1-1 Direct Addressing
    336
    
    Figure B.1-2 Extended Addressing
    336
    
    Figure B.1-3 Bit Direct Addressing
    337
    
    Figure B.1-4 Index Addressing
    337
    
    Figure B.1-5 Pointer Addressing
    337
    
    Figure B.1-6 General-Purpose Register Addressing
    338
    
    Figure B.1-7 Immediate Addressing
    338
  - Table B.1-1 Vector Table Addresses Corresponding to "Vct
    338
    
    Figure B.1-10 Inherent Addressing
    339
    
    Figure B.2-1 JMP @A
    340
    
    Figure B.2-2 MOVW A, PC
    340
    
    Special Instructions
    340
    
    Figure B.2-3 MULU a
    341
    
    Figure B.2-4 DIVU a
    341
    
    Figure B.2-5 XCHW A,PC
    342
    
    Figure B.2-6 Example Using XCHW A,PC
    342
    
    Figure B.2-7 Execution Example of CALLV #3
    343
    
    Bit Manipulation Instructions (SETB, CLRB)
    344
  - Figure B.1-8 Vector Addressing
    339
  - Figure B.1-9 Relative Addressing
    339
  - Table B.3-1 Bus Operation for Bit Manipulation Instructions
    344
    
    F 2 MC-8L Instructions
    345
  - Table B.4-1 Transfer Instructions
    345
  - Table B.4-2 Arithmetic Operation Instructions
    346
  - Table B.4-3 Branch Instructions
    348
  - Table B.4-4 Other Instructions
    349
  - Table B.4-5 Instruction List Columns
    349
    
    Instruction Map
    351
  - Table B.5-1 F2MC-8L Instruction Map
    351
- APPENDIX C Mask Options
  
  353
  - Table C-1 Mask Options List
    353
  - Table C-2 Standard Options
    354
  - Table C-3 Ordering Information
    354
- APPENDIX D Programming PROM
  
  355
- APPENDIX Emb89120 Series Pin States
  
  363
Index

366

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