Fujitsu F2MC-8L Series Hardware Manual page 229

CHAPTER 8 8-BIT SERIAL I/O
Table 8.4-1 Serial Mode Register (SMR) Bits (Continued)
Bit
SST:
Bit 0
Serial I/O transfer start bit
202
• This bit controls serial I/O transfer start and transfer enable. This
bit can also be used to determine whether transfer has completed.
• Writing "1" to this bit when an internal shift clock is selected (CKS1,
CKS0 = other than "11
data transfer.
• Writing "1" to this bit when an external shift clock is selected
(CKS1, CKS0 = "11
counter, and sets serial I/O to delay for input of the external shift
clock.
• This bit is cleared to "0" and the SIOF bit set to "1" when transfer
completes.
• Writing "0" to this bit while transfer is in progress (SST = "1") aborts
the transfer. After halting a transfer, data must be set again to the
SDR register for data output and transfer must be restarted (the
shift clock counter cleared) for data input.
Function
") clears the shift clock counter and starts
B
") enables data transfer, clears the shift clock
B