Fujitsu F2MC-8L Series Hardware Manual page 332

Table A-1 I/O Map (Continued)
Register
Address
name
16
H
17
H
18 T2CR
H
19 T1CR
H
1A T2DR
H
1B T1DR
H
1C SMR
H
1D SDR
H
1E
H
to
21
H
22
H
23 EIC1
H
24 EIC1
H
25 to 31
H H
32 EIE2
H
33 EIF2
H
34
H
to
7B
H
7C ILR1
H
7D ILR2
H
7E ILR3
H
7F
H
*: MB89120A series only
Register description
(Vacancy)
Timer 2 control register
Timer 1 register
Timer 2 data register
Timer 1 data register
Serial mode register
Serial ata register
(Vacancy)
(Vacancy)
External interrupt 1control register 1
External interrupt 1control register 2
(Vacancy)
External interrupt 2 control register *
External interrupt 2 flag register *
(Vacancy)
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
(Vacancy)
APPENDIX A I/O Map
Read/Write Initial value
XXXXXXXX
R/W X000XXX0
R/W X000XXX0
R/W XXXXXXXX
R/W XXXXXXXX
R/W 00000000
R/W XXXXXXXX
XXXXXXXX
XXXXXXXX
R/W 00000000
R/W XXXX0000
XXXXXXXX
R/W 00000000
R/W XXXXXXX0
XXXXXXXX
W 11111111
W 11111111
W 11111111
XXXXXXXX
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
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