Instruction Execution Timing; Reset And Interrupt Handling - Atmel ATtiny25 Manual

4.7

Instruction Execution Timing

4.8

Reset and Interrupt Handling

7598H–AVR–07/09
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-5. Single Cycle ALU Operation
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0.
, directly generated from the selected clock source for the
CPU
T1 T2
T1 T2
"Interrupts" on page
ATtiny25/45/85
T3 T4
T3 T4
45. The list also
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