Reset And Interrupt Handling - Atmel AVR AT90S2333 Manual

instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or
return from interrupt RETI.

Reset and Interrupt Handling

The AT90S2333/4433 provides 13 different interrupt sources. These interrupts and the separate reset vector, each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0, etc.
Table 3. Reset and Interrupt Vectors
Vector No. Program Address
1 $000
2 $001
3 $002
4 $003
5 $004
6 $005
7 $006
8 $007
9 $008
10 $009
11 $00A
12 $00B
13 $00C
14 $00D
The most typical program setup for the Reset and Interrupt Vector Addresses are:
Address
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00a
$00b
$00c
$00d
;
AT90S/LS2333 and AT90S/LS4433
18
Source
RESET
INT0
INT1
TIMER1 CAPT
TIMER1 COMP
TIMER1 OVF
TIMER0 OVF
SPI, STC
UART, RX
UART, UDRE
UART, TX
ADC
EE_RDY
ANA_COMP
Labels Code
rjmp RESET
rjmp EXT_INT0
rjmp EXT_INT1
rjmp TIM1_CAPT
rjmp TIM1_COMP
rjmp TIM1_OVF
rjmp TIM0_OVF
rjmp SPI_STC;
rjmp UART_RXC
rjmp UART_DRE
rjmp UART_TXC
rjmp ADC
rjmp EE_RDY
rjmp ANA_COMP
Interrupt Definition
External Pin, Power-On Reset, Brown-Out Reset and Watchdog Reset.
External Interrupt Request 0
External Interrupt Request 1
Timer/Counter1 Capture Event
Timer/Counter1 Compare Match
Timer/Counter1 Overflow
Timer/Counter0 Overflow
Serial Transfer Complete
UART, Rx Complete
UART Data Register Empty
UART, Tx Complete
ADC Conversion Complete
EEPROM Ready
Analog Comparator
Comments
; Reset Handler
; IRQ0 Handler
; IRQ1 Handler
; Timer1 Capture Handler
; Timer1 compare Handler
; Timer1 Overflow Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; UART RX Complete Handler
; UDR Empty Handler
; UART TX Complete Handler
; ADC Conversion Complete Interrupt Handler
; EEPROM Ready Handler
; Analog Comparator Handler