Video Display Frame Size Register (Vdfrmsz); Video Display Horizontal Blanking Register (Vdhblnk); Video Display Frame Size Register (Vdfrmsz) Field Descriptions - Texas Instruments TMS320DM648 User Manual

Video port/vcxo interpolated control (vic) port
Hide thumbs Also See for TMS320DM648:
Table of Contents

Advertisement

www.ti.com

4.12.3 Video Display Frame Size Register (VDFRMSZ)

The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the
ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT).
The FPCOUNT starts at 0 and counts to FRMWIDTH - 1 before restarting. The FLCOUNT starts at 1 and
counts to FRMHEIGHT before restarting.
The video display frame size register (VDFRMSZ) is shown in
31
28
Reserved
R-0
15
12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-8. Video Display Frame Size Register (VDFRMSZ) Field Descriptions
(1)
Bit
field
symval
31-28 Reserved
-
27-16 FRMHEIGHT
OF(value)
DEFAULT
15-12 Reserved
-
11-0
FRMWIDTH
OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_VDFRMSZ_field_symval

4.12.4 Video Display Horizontal Blanking Register (VDHBLNK)

The video display horizontal blanking register (VDHBLNK) controls the display horizontal blanking.
Every time the frame pixel counter (FPCOUNT) is equal to HBLNKSTART, HBLNK is asserted.
HBLNKSTART also determines where the EAV code is inserted in the BT.656 and Y/C output.
Every time FPCOUNT = HBLNKSTOP, the HBLNK signal is de-asserted (this is shown in
BT.656 and Y/C modes, HBLNKSTOP determines the SAV code insertion point and HBLNK de-assertion
point. The HBLNK inactive edge may optionally be delayed by 4 pixel clocks using the HBDLA bit.
The video display horizontal blanking register (VDHBLNK) is shown in
Table 4-9
SPRUEM1 – May 2007
Submit Documentation Feedback
Figure 4-33. Video Display Frame Size Register (VDFRMSZ)
27
11
(1)
Value
Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh
Defines the total number of lines per frame. The number is the ending value of the
frame line counter (FLCOUNT).
For BT.656 operation, the FRMHIGHT is set to 525 (525/60 operation) or 625
(625/50 operation).
0
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh
Defines the total number of pixels per line including blanking. The number is the
frame pixel counter (FPCOUNT) ending value + 1.
For BT.656 operation, the FRMWIDTH is typically 858 or 864.
0
Figure 4-33
and described in
FRMHEIGHT
R/W-0
FRMWIDTH
R/W-0
Figure 4-34
and described in
Video Display Registers
Table
4-8.
16
0
Figure
4-5). In
Video Display Port
127

Advertisement

Table of Contents
loading

This manual is also suitable for:

Tms320dm647

Table of Contents